ENGR00223797-11 MX6 clock:Protect IPU1 related clock tree

This patch enables IPU1 related clocks by default if CONFIG_
MX6_CLK_FOR_BOOTUI_TRANS is set, to support smooth UI tran-
sition from bootloader to kernel and keeps the specific trees
(told in below) unchanged. The kernel assumes that the boot-
loader uses IPU1 DI1 and LDB DI1 to driver a LVDS display
panel to do splashimage. LDB should works in separate mode
or single mode. The IPU1 related clock trees are:
1) MX6DQ SabreSD:
 ipu1_clk --
   osc_clk(24M)->pll2_528_bus_main_clk(528M)->periph_clk(528M)
   ->mmdc_ch0_axi_clk(528M)->ipu1_clk(264M)

 ipu1_pixel_clk_1 --
   osc_clk(24M)->pll2_528_bus_main_clk(528M)->
   pll2_pfd_352M(452.57M)->ldb_di1_clk(64.65M)->
   ipu1_di_clk_1(64.65M)->ipu1_pixel_clk_1(64.65M)

2) MX6DL SabreSD:
 ipu1_clk --
   osc_clk(24M)->pll3_usb_otg_main_clk(480M)->
   pll3_pfd_540M(540M)->ipu1_clk(270M)

 ipu1_pixel_clk_1 --
   osc_clk(24M)->pll2_528_bus_main_clk(528M)->
   pll2_pfd_352M(452.57M)->ldb_di1_clk(64.65M)->
   ipu1_di_clk_1(64.65M)->ipu1_pixel_clk_1(64.65M)

So for MX6DQ and MX6DL, with CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
set, this patch keeps ipu1_clk, ldb_di1_clk, ipu1_di_clk_1 and
pll2_pfd_352M being enabled and keeps ipu1_di_clk_1's parent
unchanged. And, for MX6DL, with CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
set this patch keeps pll3_usb_otg_main_clk and pll3_pfd_540M
being enabled.  This patch is for Android kernel only.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit fea14a67c254e428fc241a3f3165a3ec9f814076)

1 files changed, 39 insertions, 3 deletions

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 4b5bd3071af5..54da94417a0d 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5374,16 +5374,34 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 	/* Disable un-necessary PFDs & PLLs */
 	if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q())
 		pll2_pfd_400M.disable(&pll2_pfd_400M);
+#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+	/*
+	 * Bootloader may use pll2_pfd_352M to drive ldb_di1_clk
+	 * to support splashimage so we should not disable the
+	 * clock to keep the display running.
+	 */
 	pll2_pfd_352M.disable(&pll2_pfd_352M);
+#endif
 	pll2_pfd_594M.disable(&pll2_pfd_594M);
 
 #if !defined(CONFIG_FEC_1588)
 	pll3_pfd_454M.disable(&pll3_pfd_454M);
 	pll3_pfd_508M.disable(&pll3_pfd_508M);
-	pll3_pfd_540M.disable(&pll3_pfd_540M);
 	pll3_pfd_720M.disable(&pll3_pfd_720M);
-
-	pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
+	if (cpu_is_mx6q()) {
+		pll3_pfd_540M.disable(&pll3_pfd_540M);
+		pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
+	} else if (cpu_is_mx6dl()) {
+#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+		/*
+		 * Bootloader may use pll3_pfd_540M to drive ipu1_clk
+		 * to support splashimage so we should not disable the
+		 * clock to keep the display running.
+		 */
+		pll3_pfd_540M.disable(&pll3_pfd_540M);
+		pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
+#endif
+	}
 #endif
 	pll4_audio_main_clk.disable(&pll4_audio_main_clk);
 	pll5_video_main_clk.disable(&pll5_video_main_clk);
@@ -5398,8 +5416,16 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 	clk_set_rate(&pll4_audio_main_clk, 176000000);
 	clk_set_rate(&pll5_video_main_clk, 650000000);
 
+	/*
+	 * We don't set ipu1_di_clk[1]'s parent clock to
+	 * pll5_video_main_clk as bootloader may need
+	 * the parent to be ldb_di1_clk to support LVDS
+	 * panel splashimage.
+	 */
 	clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
+#ifndef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
 	clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
+#endif
 	clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
 	clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
 
@@ -5496,6 +5522,16 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
 		     1 << MXC_CCM_CCGRx_CG13_OFFSET |
 		     3 << MXC_CCM_CCGRx_CG12_OFFSET |
 		     1 << MXC_CCM_CCGRx_CG11_OFFSET |
+#ifdef CONFIG_MX6_CLK_FOR_BOOTUI_TRANS
+		     /*
+		      * We use IPU1 DI1 to do bootloader splashimage by
+		      * default, so we need to enable the clocks to
+		      * keep the display running.
+		      */
+		     3 << MXC_CCM_CCGRx_CG7_OFFSET |	/* ldb_di1_clk */
+		     3 << MXC_CCM_CCGRx_CG2_OFFSET |	/* ipu1_di1_clk */
+		     3 << MXC_CCM_CCGRx_CG0_OFFSET |	/* ipu1_clk */
+#endif
 		     3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
 	__raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
 			1 << MXC_CCM_CCGRx_CG6_OFFSET |