diff options
author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-02-18 20:27:06 +0800 |
---|---|---|
committer | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-02-19 18:50:07 +0800 |
commit | 0d7ac3c74923d82d474280403e32d0a233e28ff5 (patch) | |
tree | e8e8f2c3341503b8b480ae5a487462a98b3aefbd /arch | |
parent | aca9c9d8ff535d9eb8ba79f22c0ad6b8306bfa8b (diff) |
ENGR00299756-2 ARM: imx6q: Add missing lvds2 clock to the clock tree
We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.
So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.
[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff)
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index d08999b75bf2..9bc6f6166b8e 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -1,5 +1,5 @@ /* - * Copyright 2011-2013 Freescale Semiconductor, Inc. + * Copyright 2011-2014 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -73,6 +73,7 @@ static const char *cko2_sels[] = { static const char *cko_sels[] = { "cko1", "cko2", }; static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", }; +static const char *pll_av_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; enum mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, @@ -110,7 +111,8 @@ enum mx6q_clks { spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, gpt_3m, video_27m, ldb_di0_div_7, ldb_di1_div_7, ldb_di0_div_sel, ldb_di1_div_sel, pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, caam_mem, caam_aclk, - caam_ipg, epit1, epit2, tzasc2, clk_max + caam_ipg, epit1, epit2, tzasc2, pll4_sel, lvds2_sel, lvds2_in, lvds2_out, + anaclk1, anaclk2, clk_max }; static struct clk *clk[clk_max]; @@ -153,6 +155,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[ckil] = imx_obtain_fixed_clock("ckil", 0); clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); clk[osc] = imx_obtain_fixed_clock("osc", 0); + /* Clock source from external clock via ANACLK1/2 PADs */ + clk[anaclk1] = imx_obtain_fixed_clock("anaclk1", 0); + clk[anaclk2] = imx_obtain_fixed_clock("anaclk2", 0); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); base = of_iomap(np, 0); @@ -170,13 +175,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f, false); clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1, false); clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3, false); - clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f, false); + clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "pll4_sel", base + 0x70, 0x7f, false); clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f, false); clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3, false); clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3, false); /* name reg shift width parent_names num_parents */ clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); + clk[pll4_sel] = imx_clk_mux("pll4_sel", base + 0x70, 14, 2, pll_av_sels, ARRAY_SIZE(pll_av_sels)); /* * Bit 20 is the reserved and read-only bit, we do this only for: @@ -196,9 +203,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); - /* NOTICE: The gate of the lvds1 in/out is used to select the clk direction */ - clk[lvds1_in] = imx_clk_gate("lvds1_in", NULL, base + 0x160, 12); + /* NOTICE: The gate of the lvds1/2 in/out is used to select the clk direction */ + clk[lvds1_in] = imx_clk_gate("lvds1_in", "anaclk1", base + 0x160, 12); + clk[lvds2_in] = imx_clk_gate("lvds2_in", "anaclk2", base + 0x160, 13); clk[lvds1_out] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10); + clk[lvds2_out] = imx_clk_gate("lvds2_out", "lvds2_sel", base + 0x160, 11); clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); |