diff options
| author | Xinyu Chen <xinyu.chen@freescale.com> | 2012-04-20 11:28:57 +0800 |
|---|---|---|
| committer | Xinyu Chen <xinyu.chen@freescale.com> | 2012-04-20 11:28:57 +0800 |
| commit | eb1da050c08bb961a1e45dd51f97821d3eeb2ae9 (patch) | |
| tree | 543a339d5395485a5a2d99f91e42c817a147b461 /arch | |
| parent | 8e3395a73276d41082c35e2af21d44dbd3d648ff (diff) | |
| parent | 2914e50b00af66d52eac98fa58e4f4f159a2305b (diff) | |
Merge branch 'android-3.0' into imx_3.0.15_android
Conflicts:
drivers/cpufreq/cpufreq_interactive.c
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 089c0b5e454f..b6ba1032a988 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -270,10 +270,6 @@ cpu_resume_l1_flags: * Initialise TLB, Caches, and MMU state ready to switch the MMU * on. Return in r0 the new CP15 C1 control register setting. * - * We automatically detect if we have a Harvard cache, and use the - * Harvard cache control instructions insead of the unified cache - * control instructions. - * * This should be able to cover all ARMv7 cores. * * It is assumed that: @@ -363,9 +359,7 @@ __v7_setup: #endif 3: mov r10, #0 -#ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -#endif dsb #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |