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authorPaul Mundt <lethal@linux-sh.org>2006-11-05 16:48:42 +0900
committerPaul Mundt <lethal@linux-sh.org>2006-12-06 10:45:37 +0900
commit710ee0cc45d095f7697821b330a3f8280205c2be (patch)
tree8bce794be73a6961d118d485c097232628812e94 /arch
parentf36af3fd377081d3ac2ff6b63a60f8db8b3bf531 (diff)
sh: SE7206 build fixes.
A number of API changes happened underneath the 7206 patches, update for everything that broke. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/boards/se/7206/irq.c44
-rw-r--r--arch/sh/boards/se/7206/setup.c3
-rw-r--r--arch/sh/kernel/sys_sh.c2
-rw-r--r--arch/sh/kernel/timers/timer-cmt.c63
-rw-r--r--arch/sh/kernel/timers/timer-mtu2.c62
-rw-r--r--arch/sh/kernel/traps.c12
6 files changed, 34 insertions, 152 deletions
diff --git a/arch/sh/boards/se/7206/irq.c b/arch/sh/boards/se/7206/irq.c
index 8d5b278a124d..3fb0c5f5b23a 100644
--- a/arch/sh/boards/se/7206/irq.c
+++ b/arch/sh/boards/se/7206/irq.c
@@ -6,12 +6,10 @@
* Hitachi SolutionEngine Support.
*
*/
-
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/irq.h>
-#include <asm/irq.h>
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/irq.h>
#include <asm/se7206.h>
#define INTSTS0 0x31800000
@@ -20,9 +18,6 @@
#define INTMSK1 0x31800006
#define INTSEL 0x31800008
-/* shutdown is same as "disable" */
-#define shutdown_se7206_irq disable_se7206_irq
-
static void disable_se7206_irq(unsigned int irq)
{
unsigned short val;
@@ -84,18 +79,7 @@ static void enable_se7206_irq(unsigned int irq)
ctrl_outw(msk1, INTMSK1);
}
-static unsigned int startup_se7206_irq(unsigned int irq)
-{
- enable_se7206_irq(irq);
- return 0; /* never anything pending */
-}
-
-static void ack_se7206_irq(unsigned int irq)
-{
- disable_se7206_irq(irq);
-}
-
-static void end_se7206_irq(unsigned int irq)
+static void eoi_se7206_irq(unsigned int irq)
{
unsigned short sts0,sts1;
@@ -121,20 +105,19 @@ static void end_se7206_irq(unsigned int irq)
ctrl_outw(sts1, INTSTS1);
}
-static struct hw_interrupt_type se7206_irq_type = {
- .typename = "SE7206 FPGA-IRQ",
- .startup = startup_se7206_irq,
- .shutdown = shutdown_se7206_irq,
- .enable = enable_se7206_irq,
- .disable = disable_se7206_irq,
- .ack = ack_se7206_irq,
- .end = end_se7206_irq,
+static struct irq_chip se7206_irq_chip __read_mostly = {
+ .name = "SE7206-FPGA-IRQ",
+ .mask = disable_se7206_irq,
+ .unmask = enable_se7206_irq,
+ .mask_ack = disable_se7206_irq,
+ .eoi = eoi_se7206_irq,
};
static void make_se7206_irq(unsigned int irq)
{
disable_irq_nosync(irq);
- irq_desc[irq].handler = &se7206_irq_type;
+ set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
+ handle_level_irq, "level");
disable_se7206_irq(irq);
}
@@ -154,8 +137,3 @@ void __init init_se7206_IRQ(void)
/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
ctrl_outw(0x0001,INTSEL);
}
-
-int se7206_irq_demux(int irq)
-{
- return irq;
-}
diff --git a/arch/sh/boards/se/7206/setup.c b/arch/sh/boards/se/7206/setup.c
index e543e3980c08..0f42e91a3238 100644
--- a/arch/sh/boards/se/7206/setup.c
+++ b/arch/sh/boards/se/7206/setup.c
@@ -10,8 +10,8 @@
#include <linux/init.h>
#include <linux/platform_device.h>
-#include <asm/io.h>
#include <asm/se7206.h>
+#include <asm/io.h>
#include <asm/machvec.h>
static struct resource smc91x_resources[] = {
@@ -72,7 +72,6 @@ struct sh_machine_vector mv_se __initmv = {
.mv_outsl = se7206_outsl,
.mv_init_irq = init_se7206_IRQ,
- .mv_irq_demux = se7206_irq_demux,
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_se,
#endif
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 8fde95001c34..07f2b5718938 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -50,6 +50,7 @@ unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
EXPORT_SYMBOL(shm_align_mask);
+#ifdef CONFIG_MMU
/*
* To avoid cache aliases, we map the shared page with same color.
*/
@@ -135,6 +136,7 @@ full_search:
addr = COLOUR_ALIGN(addr, pgoff);
}
}
+#endif /* CONFIG_MMU */
static inline long
do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
index 9eab395cd341..30687383d4b0 100644
--- a/arch/sh/kernel/timers/timer-cmt.c
+++ b/arch/sh/kernel/timers/timer-cmt.c
@@ -96,8 +96,7 @@ static unsigned long cmt_timer_get_offset(void)
return count;
}
-static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id,
- struct pt_regs *regs)
+static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id)
{
unsigned long timer_status;
@@ -114,7 +113,7 @@ static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id,
* locally disabled. -arca
*/
write_seqlock(&xtime_lock);
- handle_timer_tick(regs);
+ handle_timer_tick();
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
@@ -123,62 +122,10 @@ static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id,
static struct irqaction cmt_irq = {
.name = "timer",
.handler = cmt_timer_interrupt,
- .flags = SA_INTERRUPT,
+ .flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
};
-/*
- * Hah! We'll see if this works (switching from usecs to nsecs).
- */
-static unsigned long cmt_timer_get_frequency(void)
-{
- u32 freq;
- struct timespec ts1, ts2;
- unsigned long diff_nsec;
- unsigned long factor;
-
- /* Setup the timer: We don't want to generate interrupts, just
- * have it count down at its natural rate.
- */
-
- ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
- ctrl_outw(CMT_CMCSR_CALIB, CMT_CMCSR_0);
- ctrl_outw(0xffff, CMT_CMCOR_0);
- ctrl_outw(0xffff, CMT_CMCNT_0);
-
- rtc_sh_get_time(&ts2);
-
- do {
- rtc_sh_get_time(&ts1);
- } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
-
- /* actually start the timer */
- ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
-
- do {
- rtc_sh_get_time(&ts2);
- } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
-
- freq = 0xffff - ctrl_inw(CMT_CMCNT_0);
- if (ts2.tv_nsec < ts1.tv_nsec) {
- ts2.tv_nsec += 1000000000;
- ts2.tv_sec--;
- }
-
- diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
-
- /* this should work well if the RTC has a precision of n Hz, where
- * n is an integer. I don't think we have to worry about the other
- * cases. */
- factor = (1000000000 + diff_nsec/2) / diff_nsec;
-
- if (factor * diff_nsec > 1100000000 ||
- factor * diff_nsec < 900000000)
- panic("weird RTC (diff_nsec %ld)", diff_nsec);
-
- return freq * factor;
-}
-
static void cmt_clk_init(struct clk *clk)
{
u8 divisor = CMT_CMCSR_INIT & 0x3;
@@ -245,12 +192,12 @@ struct sys_timer_ops cmt_timer_ops = {
.init = cmt_timer_init,
.start = cmt_timer_start,
.stop = cmt_timer_stop,
- .get_frequency = cmt_timer_get_frequency,
+#ifndef CONFIG_GENERIC_TIME
.get_offset = cmt_timer_get_offset,
+#endif
};
struct sys_timer cmt_timer = {
.name = "cmt",
.ops = &cmt_timer_ops,
};
-
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
index 73a5ef3c457d..045b2aba13fa 100644
--- a/arch/sh/kernel/timers/timer-mtu2.c
+++ b/arch/sh/kernel/timers/timer-mtu2.c
@@ -98,8 +98,7 @@ static unsigned long mtu2_timer_get_offset(void)
return count;
}
-static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id,
- struct pt_regs *regs)
+static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
{
unsigned long timer_status;
@@ -110,7 +109,7 @@ static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id,
/* Do timer tick */
write_seqlock(&xtime_lock);
- handle_timer_tick(regs);
+ handle_timer_tick();
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
@@ -119,62 +118,10 @@ static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id,
static struct irqaction mtu2_irq = {
.name = "timer",
.handler = mtu2_timer_interrupt,
- .flags = SA_INTERRUPT,
+ .flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
};
-/*
- * Hah! We'll see if this works (switching from usecs to nsecs).
- */
-static unsigned long mtu2_timer_get_frequency(void)
-{
- u32 freq;
- struct timespec ts1, ts2;
- unsigned long diff_nsec;
- unsigned long factor;
-
- /* Setup the timer: We don't want to generate interrupts, just
- * have it count down at its natural rate.
- */
-
- ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
- ctrl_outb(MTU2_TCR_CALIB, MTU2_TCR_1);
- ctrl_outb(ctrl_inb(MTU2_TIER_1) & ~MTU2_TIER_TGIEA, MTU2_TIER_1);
- ctrl_outw(0, MTU2_TCNT_1);
-
- rtc_get_time(&ts2);
-
- do {
- rtc_get_time(&ts1);
- } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
-
- /* actually start the timer */
- ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
-
- do {
- rtc_get_time(&ts2);
- } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
-
- freq = ctrl_inw(MTU2_TCNT_0);
- if (ts2.tv_nsec < ts1.tv_nsec) {
- ts2.tv_nsec += 1000000000;
- ts2.tv_sec--;
- }
-
- diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
-
- /* this should work well if the RTC has a precision of n Hz, where
- * n is an integer. I don't think we have to worry about the other
- * cases. */
- factor = (1000000000 + diff_nsec/2) / diff_nsec;
-
- if (factor * diff_nsec > 1100000000 ||
- factor * diff_nsec < 900000000)
- panic("weird RTC (diff_nsec %ld)", diff_nsec);
-
- return freq * factor;
-}
-
static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
static void mtu2_clk_init(struct clk *clk)
@@ -250,8 +197,9 @@ struct sys_timer_ops mtu2_timer_ops = {
.init = mtu2_timer_init,
.start = mtu2_timer_start,
.stop = mtu2_timer_stop,
- .get_frequency = mtu2_timer_get_frequency,
+#ifndef CONFIG_GENERIC_TIME
.get_offset = mtu2_timer_get_offset,
+#endif
};
struct sys_timer mtu2_timer = {
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 1edec2709efe..f558748d7543 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -107,8 +107,6 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs,
die(str, regs, err);
}
-static int handle_unaligned_notify_count = 10;
-
/*
* try and fix up kernelspace address errors
* - userspace errors just cause EFAULT to be returned, resulting in SEGV
@@ -347,6 +345,13 @@ static inline int handle_unaligned_delayslot(struct pt_regs *regs)
#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
+/*
+ * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
+ * opcodes..
+ */
+#ifndef CONFIG_CPU_SH2A
+static int handle_unaligned_notify_count = 10;
+
static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
{
u_int rm;
@@ -483,6 +488,7 @@ static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
regs->pc += 2;
return ret;
}
+#endif /* CONFIG_CPU_SH2A */
#ifdef CONFIG_CPU_HAS_SR_RB
#define lookup_exception_vector(x) \
@@ -501,8 +507,10 @@ asmlinkage void do_address_error(struct pt_regs *regs,
{
unsigned long error_code = 0;
mm_segment_t oldfs;
+#ifndef CONFIG_CPU_SH2A
u16 instruction;
int tmp;
+#endif
/* Intentional ifdef */
#ifdef CONFIG_CPU_HAS_SR_RB