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authorSachin Nikam <snikam@nvidia.com>2011-09-21 18:14:35 +0530
committerRohan Somvanshi <rsomvanshi@nvidia.com>2011-09-27 05:36:29 -0700
commit888142aa547970174dd5587cd88788652b5be93a (patch)
treef88fd6b0f8f320cde3d6499b01b34037de7ca9f8 /arch
parent98d70cfd0f077c9e8af2481c3fde6720e1d7a636 (diff)
ARM: tegra: increasing sdmmc4 clock freq to 48MHz
Change-Id: I5004283c2aae7b5f6726f1f689ea4454c12e6139 Signed-off-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/53761 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/common.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 74d9eed96bfd..2eb249c71e7a 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -163,7 +163,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "pll_u", NULL, 480000000, false },
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
- { "sdmmc4", "clk_m", 12000000, true},
+ { "sdmmc4", "pll_p", 48000000, true},
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
{ "cbus", "pll_c", 416000000, false },
{ "pll_c_out1", "pll_c", 208000000, false },