diff options
| author | Yong Goo Yi <yyi@nvidia.com> | 2014-01-27 20:15:06 +0900 |
|---|---|---|
| committer | Harry Hong <hhong@nvidia.com> | 2014-01-27 22:02:50 -0800 |
| commit | 9253804dd6052bf89c7aaf45f41b174d783db66b (patch) | |
| tree | 1d301001e1c444a3fccd5cb3d41bef6dffed4ddd /arch | |
| parent | 5bc2c17e236a36bc1812fe9e56bb55e3999dd9c2 (diff) | |
ARM: tegra: tegratab: set smps7 to 1.38V for E1569
Set smps7 to 1.38V for E1569-ERS has Micron 1GB
Change-Id: I1f55e0b2bf96d6efed04e301b800a52e4d23fbb7
Signed-off-by: Yong Goo Yi <yyi@nvidia.com>
Reviewed-on: http://git-master/r/360389
Reviewed-by: Harry Hong <hhong@nvidia.com>
Tested-by: Harry Hong <hhong@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/board-tegratab-power.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/board-tegratab-power.c b/arch/arm/mach-tegra/board-tegratab-power.c index f57f178cadff..172da27c3658 100644 --- a/arch/arm/mach-tegra/board-tegratab-power.c +++ b/arch/arm/mach-tegra/board-tegratab-power.c @@ -676,10 +676,13 @@ int __init tegratab_palmas_regulator_init(void) tegra_get_board_info(&board_info); - if (board_info.board_id == BOARD_P1640 && + if ((board_info.board_id == BOARD_E1569) || + (board_info.board_id == BOARD_P1640 && ((board_info.fab < BOARD_FAB_A04) || (board_info.fab >= BOARD_FAB_A04 && - tegra_bct_strapping != 1))) { + tegra_bct_strapping != 1))) || + (board_info.board_id == BOARD_P1988 && + tegra_bct_strapping == 0)) { /* Boot strapping 0, 2, 3 indicate Micron 1GB MT41K128M16-125 * and it requires VDDIO_DDR 1.38V for stability. * Boot strapping 1 indicates Hynix 1GB H5TC2G63FFR-PBA and @@ -689,11 +692,6 @@ int __init tegratab_palmas_regulator_init(void) 1380000; tegratab_reg_data[PALMAS_REG_SMPS7]->constraints.max_uV = 1380000; - } else if (board_info.board_id == BOARD_P1988) { - tegratab_reg_data[PALMAS_REG_SMPS7]->constraints.min_uV = - 1380000; - tegratab_reg_data[PALMAS_REG_SMPS7]->constraints.max_uV = - 1380000; } if ((board_info.board_id == BOARD_P1640 && |