diff options
| author | Pawel Moll <pawel.moll@arm.com> | 2011-05-20 14:39:29 +0100 |
|---|---|---|
| committer | Ann Thornton <ann.thornton@freescale.com> | 2012-03-22 14:19:09 -0500 |
| commit | 487fbf229ce67173c69a31d936128459b30674e4 (patch) | |
| tree | 2468a63db1e0fd08344fede5cae4e5d9cbf7a91b /arch | |
| parent | c0a11ac5e664cc6181e20e9fbccdc6b811a7f50c (diff) | |
ARM: proc: add Cortex-A5 proc info
This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 15eb169bfec291faf25b158cfa9842b72f7803ad)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 6f9013373a98..18d91a8229ad 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -279,6 +279,7 @@ cpu_resume_l1_flags: * It is assumed that: * - cache type register is implemented */ +__v7_ca5mp_setup: __v7_ca9mp_setup: #ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @@ -465,6 +466,16 @@ cpu_elf_name: .endm /* + * ARM Ltd. Cortex A5 processor. + */ + .type __v7_ca5mp_proc_info, #object +__v7_ca5mp_proc_info: + .long 0x410fc050 + .long 0xff0ffff0 + __v7_proc __v7_ca5mp_setup + .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info + + /* * ARM Ltd. Cortex A9 processor. */ .type __v7_ca9mp_proc_info, #object |