diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-03-10 12:01:17 -0700 |
|---|---|---|
| committer | Harry Hong <hhong@nvidia.com> | 2014-03-16 22:16:44 -0700 |
| commit | 6e2189fdf27d5cc8a5c2746a20fcca471a3e571e (patch) | |
| tree | 193cfc58e32e3237f92a8e2cb3c78b54172ec6cf /arch | |
| parent | 43d2636bc5ef882fef2cb34277cc291beef0039e (diff) | |
ARM: tegra11: clock: Use exact PLL rate in resume
Removed 1Hz margin from target rate request during PLL resume.
Although the PLL output rate is restored correctly in any case, PLL
dividers settings may differ from tabulated targets (if any) when non
exact rate is requested.
Bug 1473597
Change-Id: I5307ee49fcac4ce6dc6b3c38d1841629060700d7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/379620
(cherry-picked from 96a02b52db51498756967864d9c5a3596f812570)
Reviewed-on: http://git-master/r/381927
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Pu <dpu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Harry Hong <hhong@nvidia.com>
Tested-by: Harry Hong <hhong@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra11_clocks.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c index 6b3b82c286d7..2325b171a5f3 100644 --- a/arch/arm/mach-tegra/tegra11_clocks.c +++ b/arch/arm/mach-tegra/tegra11_clocks.c @@ -2651,7 +2651,7 @@ static void tegra11_pllcx_clk_resume_enable(struct clk *c) c->state = OFF; pllcx_set_defaults(c, rate, c->mul); - rate = clk_get_rate_all_locked(c) + 1; + rate = clk_get_rate_all_locked(c); tegra11_pllcx_clk_set_rate(c, rate); tegra11_pllcx_clk_enable(c); c->state = state; @@ -2944,7 +2944,7 @@ static void tegra11_pllxc_clk_resume_enable(struct clk *c) else pllc_set_defaults(c, rate); - rate = clk_get_rate_all_locked(c) + 1; + rate = clk_get_rate_all_locked(c); tegra11_pllxc_clk_set_rate(c, rate); tegra11_pllxc_clk_enable(c); c->state = state; @@ -3346,7 +3346,7 @@ static void tegra11_pllre_clk_resume_enable(struct clk *c) pllre_set_defaults(c->parent, rate); /* restore PLLRE VCO feedback loop (m, n) */ - rate = clk_get_rate_all_locked(c->parent) + 1; + rate = clk_get_rate_all_locked(c->parent); tegra11_pllre_clk_set_rate(c->parent, rate); /* restore PLLRE post-divider */ |