diff options
author | Bibek Basu <bbasu@nvidia.com> | 2012-10-11 12:03:18 +0530 |
---|---|---|
committer | Matthew Pedro <mapedro@nvidia.com> | 2012-11-28 19:45:06 -0800 |
commit | 03c65aadf0d141033e348d01713a4fd688d949b7 (patch) | |
tree | 660720d6d3032628bcba92526c7c326e29b442f9 /arch | |
parent | fc993d9bc48f772133d8cd156c67c296477db070 (diff) |
arm: tegra: cardhu: add support for PM315
Add support for PM315
Bug 1171138
Change-Id: I2e5461c656c41d4172aca60525655cb780eaa17e
Original-author: Mike Thompson <mikthompson@nvidia.com>
Signed-off-by: Mike Thompson <mikthompson@nvidia.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/143506
(cherry picked from commit 4e66142b6990ca586e085aa88ae0bd6b819da0c4)
Reviewed-on: http://git-master/r/166814
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu-kbc.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu-memory.c | 607 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu-pinmux.c | 67 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu-power.c | 39 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu-sensors.c | 48 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu.c | 81 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu.h | 7 |
7 files changed, 819 insertions, 33 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-kbc.c b/arch/arm/mach-tegra/board-cardhu-kbc.c index ce9b22cc1170..5bbb27176159 100644 --- a/arch/arm/mach-tegra/board-cardhu-kbc.c +++ b/arch/arm/mach-tegra/board-cardhu-kbc.c @@ -86,7 +86,8 @@ int __init cardhu_kbc_init(void) tegra_get_board_info(&board_info); if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) return 0; pr_info("Registering tegra-kbc\n"); diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c index 4ec8839c44f6..1ea30fe74a6d 100644 --- a/arch/arm/mach-tegra/board-cardhu-memory.c +++ b/arch/arm/mach-tegra/board-cardhu-memory.c @@ -24,6 +24,608 @@ #include "tegra3_emc.h" #include "fuse.h" +static const struct tegra_emc_table cardhu_emc_tables_h5tc4g83mfr[] = { + { + 0x32, /* Rev 3.2 */ + 51000, /* SDRAM frequency */ + { + 0x00000002, /* EMC_RC */ + 0x0000000d, /* EMC_RFC */ + 0x00000001, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000009, /* EMC_QSAFE */ + 0x0000000b, /* EMC_RDV */ + 0x00000181, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000000e, /* EMC_TXSR */ + 0x0000000e, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000002, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000018e, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00004288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00010003, /* MC_EMEM_ARB_CFG */ + 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 102000, /* SDRAM frequency */ + { + 0x00000004, /* EMC_RC */ + 0x0000001a, /* EMC_RFC */ + 0x00000003, /* EMC_RAS */ + 0x00000001, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000001, /* EMC_RD_RCD */ + 0x00000001, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000009, /* EMC_QSAFE */ + 0x0000000b, /* EMC_RDV */ + 0x00000303, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000001c, /* EMC_TXSR */ + 0x0000001c, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000031c, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00004288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000001, /* MC_EMEM_ARB_CFG */ + 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 204000, /* SDRAM frequency */ + { + 0x00000009, /* EMC_RC */ + 0x00000035, /* EMC_RFC */ + 0x00000007, /* EMC_RAS */ + 0x00000002, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000002, /* EMC_RD_RCD */ + 0x00000002, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000009, /* EMC_QSAFE */ + 0x0000000b, /* EMC_RDV */ + 0x00000607, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000038, /* EMC_TXSR */ + 0x00000038, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000007, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000638, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00004288, /* EMC_FBIO_CFG5 */ + 0x004400a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000003, /* MC_EMEM_ARB_CFG */ + 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 400000, /* SDRAM frequency */ + { + 0x00000012, /* EMC_RC */ + 0x00000066, /* EMC_RFC */ + 0x0000000c, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000a, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x00000006, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x0000000a, /* EMC_QSAFE */ + 0x0000000d, /* EMC_RDV */ + 0x00000bf0, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000008, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000006c, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x0000000c, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000c30, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x001d0084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00038000, /* EMC_DLL_XFORM_DQS0 */ + 0x00038000, /* EMC_DLL_XFORM_DQS1 */ + 0x00038000, /* EMC_DLL_XFORM_DQS2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS3 */ + 0x00038000, /* EMC_DLL_XFORM_DQS4 */ + 0x00038000, /* EMC_DLL_XFORM_DQS5 */ + 0x00038000, /* EMC_DLL_XFORM_DQS6 */ + 0x00038000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00030000, /* EMC_DLL_XFORM_DQ0 */ + 0x00030000, /* EMC_DLL_XFORM_DQ1 */ + 0x00030000, /* EMC_DLL_XFORM_DQ2 */ + 0x00030000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000006, /* MC_EMEM_ARB_CFG */ + 0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff89, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80000521, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200000, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 800000, /* SDRAM frequency */ + { + 0x00000025, /* EMC_RC */ + 0x000000ee, /* EMC_RFC */ + 0x0000001a, /* EMC_RAS */ + 0x00000009, /* EMC_RP */ + 0x00000005, /* EMC_R2W */ + 0x0000000d, /* EMC_W2R */ + 0x00000004, /* EMC_R2P */ + 0x00000013, /* EMC_W2P */ + 0x00000009, /* EMC_RD_RCD */ + 0x00000009, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000b, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x0000000b, /* EMC_QSAFE */ + 0x00000012, /* EMC_RDV */ + 0x00001820, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003, /* EMC_PDEX2WR */ + 0x00000012, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000f, /* EMC_AR2PDEN */ + 0x00000018, /* EMC_RW2PDEN */ + 0x000000f8, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000005, /* EMC_TCKE */ + 0x00000018, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000007, /* EMC_TCLKSTABLE */ + 0x00000008, /* EMC_TCLKSTOP */ + 0x00001860, /* EMC_TREFBW */ + 0x0000000c, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0xf0070191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000c00a, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x22220000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f501, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x06000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ + 0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff49, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80000d71, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200018, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + } +}; static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = { { @@ -6798,7 +7400,6 @@ int cardhu_emc_init(void) struct board_info board; tegra_get_board_info(&board); - switch (board.board_id) { case BOARD_PM269: tegra_init_dram_bit_map(pm269_bit_swap_map, @@ -6819,6 +7420,10 @@ int cardhu_emc_init(void) tegra_init_emc(cardhu_emc_tables_h5tc2g_pm311, ARRAY_SIZE(cardhu_emc_tables_h5tc2g_pm311)); break; + case BOARD_PM315: + tegra_init_emc(cardhu_emc_tables_h5tc4g83mfr, + ARRAY_SIZE(cardhu_emc_tables_h5tc4g83mfr)); + break; default: if (tegra_get_revision() == TEGRA_REVISION_A01) tegra_init_emc(cardhu_emc_tables_h5tc2g, diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c index 346dccfd715b..c416d453e960 100644 --- a/arch/arm/mach-tegra/board-cardhu-pinmux.c +++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c @@ -497,6 +497,20 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_e1291_a04[] = { DEFAULT_PINMUX(GPIO_PU4, RSVD1, PULL_UP, NORMAL, INPUT), }; +static __initdata struct tegra_pingroup_config cardhu_pinmux_pm315[] = { + DEFAULT_PINMUX(GMI_AD15, NAND, PULL_DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MOSI, SPI6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, RSVD1, NORMAL, NORMAL, OUTPUT), + /* PCIE dock detect */ + DEFAULT_PINMUX(GPIO_PU4, RSVD1, PULL_UP, NORMAL, INPUT), + /* CDC enable for realtek RTL5640 */ + DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT), + /* Power up for USB1, USB3 */ + DEFAULT_PINMUX(GMI_AD13, NAND, PULL_UP, NORMAL, INPUT), +}; + static __initdata struct tegra_pingroup_config cardhu_pinmux_e1198[] = { DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT), @@ -606,10 +620,33 @@ static __initdata struct tegra_pingroup_config gmi_pins_269[] = { DEFAULT_PINMUX(GMI_WP_N, NAND, NORMAL, NORMAL, INPUT), }; -static void __init cardhu_pinmux_audio_init(void) +static void __init cardhu_wm8903_audio_init(void) +{ + int ret = gpio_request(TEGRA_GPIO_CDC_IRQ, "wm8903"); + if (ret < 0) + pr_err("%s() Error in gpio_request() for gpio %d\n", + __func__, ret); + ret = gpio_direction_input(TEGRA_GPIO_CDC_IRQ); + if (ret < 0) { + pr_err("%s() Error in setting gpio %d to in/out\n", + __func__, ret); + gpio_free(TEGRA_GPIO_CDC_IRQ); + } +} + +static void __init beaver_rt5640_audio_init(void) { - gpio_request(TEGRA_GPIO_CDC_IRQ, "wm8903"); - gpio_direction_input(TEGRA_GPIO_CDC_IRQ); + int ret = gpio_request(TEGRA_GPIO_RTL_CDC_IRQ, "rt5640"); + if (ret < 0) + pr_err("%s() Error in gpio_request() for gpio %d\n", + __func__, ret); + ret = gpio_direction_input(TEGRA_GPIO_RTL_CDC_IRQ); + if (ret < 0) { + pr_err("%s() Error in setting gpio %d to in/out\n", + __func__, ret); + gpio_free(TEGRA_GPIO_RTL_CDC_IRQ); + } + } #define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \ @@ -639,6 +676,13 @@ static struct gpio_init_pin_info init_gpio_mode_e1291_a04[] = { GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR2, false, 0), }; +static struct gpio_init_pin_info init_gpio_mode_pm315[] = { + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD6, false, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD4, false, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH5, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR2, false, 0), +}; + static void __init cardhu_gpio_init_configure(void) { struct board_info board_info; @@ -670,6 +714,10 @@ static void __init cardhu_gpio_init_configure(void) pins_info = init_gpio_mode_e1291_a04; } break; + case BOARD_PM315: + len = ARRAY_SIZE(init_gpio_mode_pm315); + pins_info = init_gpio_mode_pm315; + break; default: return; } @@ -718,7 +766,12 @@ int __init cardhu_pinmux_init(void) tegra_pinmux_config_table(cardhu_pinmux_e1291_a04, ARRAY_SIZE(cardhu_pinmux_e1291_a04)); break; - + case BOARD_PM315: + tegra_pinmux_config_table(cardhu_pinmux_cardhu_a03, + ARRAY_SIZE(cardhu_pinmux_cardhu_a03)); + tegra_pinmux_config_table(cardhu_pinmux_pm315, + ARRAY_SIZE(cardhu_pinmux_pm315)); + break; case BOARD_PM269: case BOARD_PM305: case BOARD_PM311: @@ -749,7 +802,11 @@ int __init cardhu_pinmux_init(void) break; } - cardhu_pinmux_audio_init(); + if (board_info.board_id == BOARD_PM315) + beaver_rt5640_audio_init(); + else + cardhu_wm8903_audio_init(); + return 0; } diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c index 677b38347514..db86a07778b4 100644 --- a/arch/arm/mach-tegra/board-cardhu-power.c +++ b/arch/arm/mach-tegra/board-cardhu-power.c @@ -455,12 +455,14 @@ int __init cardhu_regulator_init(void) tps62361_pdata.vsel0_def_state); } - if ((board_info.board_id == BOARD_E1291) && + if (((board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) && (board_info.sku & SKU_DCDC_TPS62361_SUPPORT)) ext_core_regulator = true; if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { if (ext_core_regulator) { tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e1198_skubit0_1); @@ -485,7 +487,8 @@ int __init cardhu_regulator_init(void) } /* E1291-A04/A05: Enable DEV_SLP and enable sleep on GPIO2 */ - if ((board_info.board_id == BOARD_E1291) && + if (((board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) && ((board_info.fab == BOARD_FAB_A04) || (board_info.fab == BOARD_FAB_A05) || (board_info.fab == BOARD_FAB_A07))) { @@ -660,6 +663,13 @@ static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = { REGULATOR_SUPPLY("vdd_i2c", "2-0033"), }; +/* Enable realtek Codec for PM315 */ +static struct regulator_consumer_supply fixed_reg_cdc_en_supply[] = { + REGULATOR_SUPPLY("cdc_en", NULL), +}; + + + static struct regulator_consumer_supply fixed_reg_en_vbrtr_supply[] = { REGULATOR_SUPPLY("vdd_vbrtr", NULL), }; @@ -748,6 +758,10 @@ FIXED_REG(1, en_5v0_a04, en_5v0, NULL, 0, 0, TPS6591X_GPIO_8, true FIXED_REG(2, en_ddr_a04, en_ddr, NULL, 1, 0, TPS6591X_GPIO_7, true, 1, 1500); FIXED_REG(3, en_3v3_sys_a04, en_3v3_sys, NULL, 0, 0, TPS6591X_GPIO_6, true, 1, 3300); +/* PM315 Rev C realtek alc5640 codec */ +FIXED_REG(23, en_cdc, cdc_en, FIXED_SUPPLY(en_3v3_sys), 0, 1, TEGRA_GPIO_PX2, true, 0, 1200); + + /* Specific to pm269 */ FIXED_REG(4, en_vdd_bl_pm269, en_vdd_bl, NULL, 0, 0, TEGRA_GPIO_PH3, true, 1, 5000); FIXED_REG(6, en_vdd_pnl1_pm269, en_vdd_pnl1, FIXED_SUPPLY(en_3v3_sys), 0, 0, TEGRA_GPIO_PW1, true, 1, 3300); @@ -962,6 +976,11 @@ static struct platform_device *fixed_reg_devs_e1198_a02[] = { ADD_FIXED_REG(en_vddio_vid_oc), }; +#define PM315_FIXED_REG \ + ADD_FIXED_REG(en_cdc), + + + /* Fixed regulator devices for PM269 */ static struct platform_device *fixed_reg_devs_pm269[] = { PM269_FIXED_REG @@ -1010,6 +1029,15 @@ static struct platform_device *fixed_reg_devs_e1291_a04[] = { E1198_FIXED_REG }; +/* Fixed regulator devices for PM315 */ +static struct platform_device *fixed_reg_devs_pm315[] = { + COMMON_FIXED_REG_E1291_A04 + E1291_A03_FIXED_REG + E1198_FIXED_REG + PM315_FIXED_REG +}; + + static bool is_display_board_dsi(u16 display_board_id) { return ((display_board_id == BOARD_DISPLAY_E1213) || @@ -1063,7 +1091,10 @@ int __init cardhu_fixed_regulator_init(void) fixed_reg_devs = fixed_reg_devs_e1198_base; } break; - + case BOARD_PM315: + nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm315); + fixed_reg_devs = fixed_reg_devs_pm315; + break; case BOARD_PM311: case BOARD_PM305: nfixreg_devs = ARRAY_SIZE(fixed_reg_devs_pm311); diff --git a/arch/arm/mach-tegra/board-cardhu-sensors.c b/arch/arm/mach-tegra/board-cardhu-sensors.c index 7e9774f290eb..365da60fa9ec 100644 --- a/arch/arm/mach-tegra/board-cardhu-sensors.c +++ b/arch/arm/mach-tegra/board-cardhu-sensors.c @@ -88,7 +88,8 @@ static int cardhu_camera_init(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { ret = gpio_request(CAM1_POWER_DWN_GPIO, "camera_power_en"); if (ret < 0) pr_err("%s: gpio_request failed for gpio %s\n", @@ -137,7 +138,8 @@ static int cardhu_left_ov5650_power_on(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { if (cardhu_vdd_2v8_cam1 == NULL) { cardhu_vdd_2v8_cam1 = regulator_get(NULL, "vdd_2v8_cam1"); @@ -164,7 +166,8 @@ static int cardhu_left_ov5650_power_on(void) mdelay(5); if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 0); mdelay(20); gpio_direction_output(OV5650_RESETN_GPIO, 0); @@ -199,7 +202,8 @@ static int cardhu_left_ov5650_power_off(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); gpio_direction_output(CAM3_POWER_DWN_GPIO, 1); @@ -281,7 +285,8 @@ static int cardhu_right_ov5650_power_on(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 0); gpio_direction_output(CAM2_POWER_DWN_GPIO, 0); @@ -342,7 +347,8 @@ static int cardhu_right_ov5650_power_off(void) /* Boards E1198 and E1291 are of Cardhu personality * and do not have TCA6416 for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); gpio_direction_output(CAM3_POWER_DWN_GPIO, 1); @@ -363,8 +369,8 @@ static void cardhu_ov5650_synchronize_sensors(void) mdelay(50); gpio_direction_output(CAM1_POWER_DWN_GPIO, 0); mdelay(50); - } - else if (board_info.board_id == BOARD_E1291) { + } else if ((board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); mdelay(50); @@ -401,7 +407,8 @@ static int cardhu_ov2710_power_on(void) /* Boards E1198 and E1291 are of Cardhu personality * and do not have TCA6416 for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { if (cardhu_vdd_cam3 == NULL) { cardhu_vdd_cam3 = regulator_get(NULL, "vdd_cam3"); if (WARN_ON(IS_ERR(cardhu_vdd_cam3))) { @@ -446,7 +453,8 @@ static int cardhu_ov2710_power_off(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); gpio_direction_output(CAM3_POWER_DWN_GPIO, 1); @@ -473,7 +481,8 @@ static int cardhu_ov5640_power_on(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 0); gpio_direction_output(CAM2_POWER_DWN_GPIO, 0); @@ -526,7 +535,8 @@ static int cardhu_ov5640_power_off(void) /* Boards E1198 and E1291 are of Cardhu personality * and donot have TCA6416 exp for camera */ if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { gpio_direction_output(CAM1_POWER_DWN_GPIO, 1); gpio_direction_output(CAM2_POWER_DWN_GPIO, 1); gpio_direction_output(CAM3_POWER_DWN_GPIO, 1); @@ -858,7 +868,8 @@ static int cardhu_nct1008_init(void) (board_info.board_id == BOARD_E1257) || (board_info.board_id == BOARD_PM269) || (board_info.board_id == BOARD_PM305) || - (board_info.board_id == BOARD_PM311)) { + (board_info.board_id == BOARD_PM311) || + (board_info.board_id == BOARD_PM315)) { nct1008_port = TEGRA_GPIO_PCC2; } else if ((board_info.board_id == BOARD_E1186) || (board_info.board_id == BOARD_E1187) || @@ -1109,7 +1120,7 @@ int __init cardhu_sensors_init(void) if (board_info.sku == BOARD_SKU_B11) i2c_register_board_info(2, cardhu_i2c2_ltr_board_info, ARRAY_SIZE(cardhu_i2c2_ltr_board_info)); - else + else if (board_info.board_id != BOARD_PM315) i2c_register_board_info(2, cardhu_i2c2_isl_board_info, ARRAY_SIZE(cardhu_i2c2_isl_board_info)); @@ -1165,19 +1176,20 @@ int __init cardhu_ov5650_late_init(void) return 0; if ((board_info.board_id == BOARD_E1198) || - (board_info.board_id == BOARD_E1291)) + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) return 0; - printk("%s: \n", __func__); + printk(KERN_INFO "%s:\n", __func__); for (i = 0; i < ARRAY_SIZE(ov5650_gpio_keys); i++) { ret = gpio_request(ov5650_gpio_keys[i].gpio, ov5650_gpio_keys[i].name); if (ret < 0) { - printk("%s: gpio_request failed for gpio #%d\n", + printk(KERN_INFO "%s: gpio_request failed for gpio #%d\n", __func__, i); goto fail; } - printk("%s: enable - %d\n", __func__, i); + printk(KERN_INFO "%s: enable - %d\n", __func__, i); gpio_direction_output(ov5650_gpio_keys[i].gpio, ov5650_gpio_keys[i].enabled); gpio_export(ov5650_gpio_keys[i].gpio, false); diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index e14e6b25d644..af6b128ab429 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -56,6 +56,7 @@ #include <mach/io.h> #include <mach/i2s.h> #include <mach/tegra_asoc_pdata.h> +#include <mach/tegra_rt5640_pdata.h> #include <mach/tegra_wm8903_pdata.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -432,8 +433,16 @@ static struct i2c_board_info __initdata cardhu_codec_max98095_info = { .platform_data = &cardhu_max98095_pdata, }; +static struct i2c_board_info __initdata rt5640_board_info = { + I2C_BOARD_INFO("rt5640", 0x1c), +}; + + static void cardhu_i2c_init(void) { + struct board_info board_info; + + tegra_get_board_info(&board_info); tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data; tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data; tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data; @@ -446,7 +455,10 @@ static void cardhu_i2c_init(void) platform_device_register(&tegra_i2c_device2); platform_device_register(&tegra_i2c_device1); - i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1); + if (board_info.board_id == BOARD_PM315) + i2c_register_board_info(4, &rt5640_board_info, 1); + else + i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1); i2c_register_board_info(4, &cardhu_codec_max98095_info, 1); i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1); @@ -830,6 +842,38 @@ static struct platform_device cardhu_audio_aic326x_device = { }, }; +static struct tegra_asoc_platform_data beaver_audio_rt5640_pdata = { + .codec_name = "rt5640.4-001c", + .codec_dai_name = "rt5640-aif1", + .gpio_spkr_en = TEGRA_GPIO_RTL_SPKR_EN, + .gpio_hp_det = TEGRA_GPIO_RTL_HP_DET, + .gpio_hp_mute = -1, + .gpio_int_mic_en = TEGRA_GPIO_RTL_INT_MIC_EN, + .gpio_ext_mic_en = -1, /* TEGRA_GPIO_EXT_MIC_EN,*/ + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + }, +}; + +static struct platform_device beaver_audio_rt5640_device = { + .name = "tegra-snd-rt5640", + .id = 0, + .dev = { + .platform_data = &beaver_audio_rt5640_pdata, + }, +}; + + static struct platform_device *cardhu_devices[] __initdata = { &tegra_pmu_device, &tegra_rtc_device, @@ -860,7 +904,6 @@ static struct platform_device *cardhu_devices[] __initdata = { &baseband_dit_device, &cardhu_bt_rfkill_device, &tegra_pcm_device, - &cardhu_audio_wm8903_device, &cardhu_audio_max98095_device, &cardhu_audio_aic326x_device, &tegra_hda_device, @@ -943,6 +986,15 @@ static const u8 config_sku2000[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +static struct platform_device *cardhu_audio_devices[] __initdata = { + &cardhu_audio_wm8903_device, + +}; + +static struct platform_device *beaver_audio_devices[] __initdata = { + &beaver_audio_rt5640_device, + +}; static struct mxt_platform_data atmel_mxt_info = { .x_line = 27, @@ -1359,10 +1411,17 @@ static void cardhu_pci_init(void) cardhu_pci_platform_data.port_status[2] = 1; cardhu_pci_platform_data.use_dock_detect = 1; cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO; + } else if (board_info.board_id == BOARD_PM315) { + cardhu_pci_platform_data.port_status[0] = 1; + cardhu_pci_platform_data.port_status[1] = 0; + cardhu_pci_platform_data.port_status[2] = 1; + cardhu_pci_platform_data.use_dock_detect = 0; + cardhu_pci_platform_data.gpio = 0; } if ((board_info.board_id == BOARD_E1186) || - (board_info.board_id == BOARD_E1187) || - (board_info.board_id == BOARD_E1291)) { + (board_info.board_id == BOARD_E1187) || + (board_info.board_id == BOARD_E1291) || + (board_info.board_id == BOARD_PM315)) { tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data; platform_device_register(&tegra_pci_device); } @@ -1428,6 +1487,9 @@ static void cardhu_sata_init(void) { } static void __init tegra_cardhu_init(void) { + struct board_info board_info; + + tegra_get_board_info(&board_info); tegra_thermal_init(&thermal_data, throttle_list, ARRAY_SIZE(throttle_list)); @@ -1442,6 +1504,17 @@ static void __init tegra_cardhu_init(void) cardhu_uart_init(); tegra_camera_init(); platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices)); + switch (board_info.board_id) { + case BOARD_PM315: + platform_add_devices(beaver_audio_devices, + ARRAY_SIZE(beaver_audio_devices)); + break; + default: + platform_add_devices(cardhu_audio_devices, + ARRAY_SIZE(cardhu_audio_devices)); + + break; + } tegra_ram_console_debug_init(); tegra_io_dpd_init(); cardhu_sdhci_init(); diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h index 3dd3d23d9414..2f8e21a6492d 100644 --- a/arch/arm/mach-tegra/board-cardhu.h +++ b/arch/arm/mach-tegra/board-cardhu.h @@ -38,6 +38,7 @@ #define BOARD_E1208 0x0C08 #define BOARD_PM305 0x0305 #define BOARD_PM311 0x030B +#define BOARD_PM315 0x030F #define BOARD_PMU_PM298 0x0262 #define BOARD_PMU_PM299 0x0263 @@ -162,6 +163,12 @@ #define TEGRA_GPIO_SPKR_EN CARDHU_GPIO_WM8903(2) #define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW2 +/* PM315 Realtek audio related GPIOs */ +#define TEGRA_GPIO_RTL_CDC_IRQ TEGRA_GPIO_PX3 +#define TEGRA_GPIO_RTL_SPKR_EN -1 +#define TEGRA_GPIO_RTL_HP_DET TEGRA_GPIO_PW2 +#define TEGRA_GPIO_RTL_INT_MIC_EN TEGRA_GPIO_PK3 + /* CAMERA RELATED GPIOs on CARDHU */ #define OV5650_RESETN_GPIO TEGRA_GPIO_PBB0 #define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 |