diff options
| author | Sanchayan Maity <maitysanchayan@gmail.com> | 2017-05-04 17:47:09 +0530 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2017-05-30 13:49:23 -0700 |
| commit | 42f45b7516eb2ce24f122382c49c2f63a6763292 (patch) | |
| tree | b77c01a62625698013f7d51807b393b164b54360 /arch | |
| parent | b8e5d21a1351bc0e45ae1762f0799b428d9993ea (diff) | |
ARM: dts: imx6qdl-apalis: Split pinctrl for usdhc1 to support 4 and 8 bit
Split the pinctrl property for usdhc1 into a 4bit SD interface
and an extension to 8bit. This is required to support the 8 bit
MMC interface on the Evaluation Board for usdhc1 and the 4 bit
SD interface on Ixora V1.1 for usdhc1.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 6e7a6b549897..388ca3f9da6c 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -980,7 +980,7 @@ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 PAD_CTRL_NO /* SD1 CD */ >; }; - pinctrl_usdhc1: usdhc1grp { + pinctrl_usdhc1_4bit: usdhc1grp_4bit { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 @@ -988,6 +988,10 @@ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + pinctrl_usdhc1_8bit: usdhc1grp_8bit { + fsl,pins = < MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 @@ -1209,7 +1213,7 @@ &usdhc1 { label = "MMC1"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; disable-wp; enable-sdio-wakeup; |