diff options
author | Amlan Kundu <akundu@nvidia.com> | 2012-01-30 15:32:59 +0530 |
---|---|---|
committer | Simone Willett <swillett@nvidia.com> | 2012-02-09 12:52:40 -0800 |
commit | 854b02d84f4fb3583b3b871b82b5fe6f18f775b6 (patch) | |
tree | 770d5756c468f454b8f1ac2cec00622ffbaa71e4 /arch | |
parent | 385778bfee40e5925128ccd5186276c32ef252f2 (diff) |
ARM: tegra: p1852: Add board support files for p1852
bug 871603
P1852 is a T30 based Automotive platform.
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/72253
(cherry picked from commit 98d50016e70a22ae7e8e109cfb6633a8fe75f905)
Change-Id: Iede9881fc1168bb6802694e233554d84adfb8f44
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/79981
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-tegra/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/mach-tegra/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852-panel.c | 135 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852-pinmux.c | 391 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852-sdhci.c | 79 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852.c | 393 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852.h | 98 |
7 files changed, 1107 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index be99c2c111a7..f811d2b203e0 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -145,6 +145,12 @@ config MACH_CARDHU help Support for NVIDIA Cardhu development platform +config MACH_P1852 + bool "P1852 board" + depends on ARCH_TEGRA_3x_SOC + help + Support for NVIDIA P1852 development platform + config MACH_TEGRA_ENTERPRISE bool "Enterprise board" depends on ARCH_TEGRA_3x_SOC diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index d6e6fbb187d8..f2566ec054af 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -161,6 +161,11 @@ obj-${CONFIG_MACH_CARDHU} += board-cardhu-powermon.o obj-${CONFIG_MACH_KAI} += board-touch-kai-synaptics-spi.o obj-${CONFIG_MACH_KAI} += board-touch-kai-raydium_spi.o +obj-${CONFIG_MACH_P1852} += board-p1852.o +obj-${CONFIG_MACH_P1852} += board-p1852-panel.o +obj-${CONFIG_MACH_P1852} += board-p1852-pinmux.o +obj-${CONFIG_MACH_P1852} += board-p1852-sdhci.o + obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise.o obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-panel.o obj-${CONFIG_MACH_TEGRA_ENTERPRISE} += board-enterprise-pinmux.o diff --git a/arch/arm/mach-tegra/board-p1852-panel.c b/arch/arm/mach-tegra/board-p1852-panel.c new file mode 100644 index 000000000000..b26ff19e87be --- /dev/null +++ b/arch/arm/mach-tegra/board-p1852-panel.c @@ -0,0 +1,135 @@ +/* + * arch/arm/mach-tegra/board-p1852-panel.c + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/resource.h> +#include <asm/mach-types.h> +#include <linux/platform_device.h> +#include <linux/nvhost.h> +#include <mach/nvmap.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/dc.h> +#include <mach/fb.h> + +#include "board.h" +#include "devices.h" + +static int p1852_panel_enable(void) +{ + return 0; +} + +static int p1852_panel_disable(void) +{ + return 0; +} + +static struct tegra_dc_mode p1852_panel_modes[] = { + { + /* 800x480@60 */ + .pclk = 32460000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 64, + .v_sync_width = 3, + .h_back_porch = 128, + .v_back_porch = 22, + .h_front_porch = 64, + .v_front_porch = 20, + .h_active = 800, + .v_active = 480, + }, +}; + +static struct tegra_fb_data p1852_fb_data = { + .win = 0, + .xres = 800, + .yres = 480, + .bits_per_pixel = 32, +}; + +static struct tegra_dc_out p1852_disp1_out = { + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .type = TEGRA_DC_OUT_RGB, + .modes = p1852_panel_modes, + .n_modes = ARRAY_SIZE(p1852_panel_modes), + .enable = p1852_panel_enable, + .disable = p1852_panel_disable, +}; + +static struct tegra_dc_platform_data p1852_disp1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &p1852_disp1_out, + .emc_clk_rate = 300000000, + .fb = &p1852_fb_data, +}; + +static struct nvmap_platform_carveout p1852_carveouts[] = { + [0] = { + .name = "iram", + .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, + .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, + .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, + .buddy_size = 0, /* no buddy allocation for IRAM */ + }, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .base = 0, /* Filled in by p1852_panel_init() */ + .size = 0, /* Filled in by p1852_panel_init() */ + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data p1852_nvmap_data = { + .carveouts = p1852_carveouts, + .nr_carveouts = ARRAY_SIZE(p1852_carveouts), +}; + +static struct platform_device *p1852_gfx_devices[] __initdata = { + &tegra_nvmap_device, + &tegra_grhost_device +}; + +int __init p1852_panel_init(void) +{ + int err; + struct resource *res; + + p1852_carveouts[1].base = tegra_carveout_start; + p1852_carveouts[1].size = tegra_carveout_size; + tegra_nvmap_device.dev.platform_data = &p1852_nvmap_data; + tegra_disp1_device.dev.platform_data = &p1852_disp1_pdata; + + res = nvhost_get_resource_byname(&tegra_disp1_device, + IORESOURCE_MEM, "fbmem"); + if (!res) { + pr_err("No memory resources\n"); + return -ENODEV; + } + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + + err = platform_add_devices(p1852_gfx_devices, + ARRAY_SIZE(p1852_gfx_devices)); + if (!err) + err = nvhost_device_register(&tegra_disp1_device); + + return err; +} diff --git a/arch/arm/mach-tegra/board-p1852-pinmux.c b/arch/arm/mach-tegra/board-p1852-pinmux.c new file mode 100644 index 000000000000..3ccc9af49b63 --- /dev/null +++ b/arch/arm/mach-tegra/board-p1852-pinmux.c @@ -0,0 +1,391 @@ +/* + * arch/arm/mach-tegra/board-p1852-pinmux.c + * + * Copyright (C) 2010-2012 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <mach/pinmux.h> +#include "board.h" +#include "board-p1852.h" +#include "gpio-names.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } +/* Setting the drive strength of pins + * hsm: Enable High speed mode (ENABLE/DISABLE) + * Schimit: Enable/disable schimit (ENABLE/DISABLE) + * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8) + * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive + * strength code. Value from 0 to 31. + * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive + * strength code. Value from 0 to 31. + * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + * pullup_slew - Driver Output Pull-Down slew control code - + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + */ +#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_##_hsm, \ + .schmitt = TEGRA_SCHMITT_##_schmitt, \ + .drive = TEGRA_DRIVE_##_drive, \ + .pull_down = TEGRA_PULL_##_pulldn_drive, \ + .pull_up = TEGRA_PULL_##_pullup_drive, \ + .slew_rising = TEGRA_SLEW_##_pulldn_slew, \ + .slew_falling = TEGRA_SLEW_##_pullup_slew, \ + } + +/* !!!FIXME!!!! Update drive strength with characterized value */ +static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { + SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* All I2C pins are driven to maximum drive strength */ + /* GEN1 I2C */ + SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* GEN2 I2C */ + SET_DRIVE(AT5, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* DDC I2C */ + SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* PWR_I2C */ + SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* SDMMC4 */ + SET_DRIVE(GME, DISABLE, ENABLE, DIV_1, 22, 18, SLOWEST, SLOWEST), + SET_DRIVE(GMF, DISABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST), + SET_DRIVE(GMG, DISABLE, ENABLE, DIV_1, 15, 6, SLOWEST, SLOWEST), + SET_DRIVE(GMH, DISABLE, ENABLE, DIV_1, 12, 6, SLOWEST, SLOWEST), +}; + +#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_DEFAULT, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_##_od, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + +static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, PULL_UP, NORMAL, INPUT), + + /* SDMMC2 pinmux */ + DEFAULT_PINMUX(KB_ROW10, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9, SDMMC2, PULL_UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, POPSDMMC4, PULL_UP, NORMAL, INPUT), + I2C_PINMUX(CAM_I2C_SCL, POPSDMMC4, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE), + I2C_PINMUX(CAM_I2C_SDA, POPSDMMC4, PULL_UP, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(GPIO_PBB3, POPSDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB4, POPSDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, POPSDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, POPSDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, POPSDMMC4, PULL_UP, NORMAL, INPUT), + + /* UART1 pinmux */ + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, OUTPUT), + + /* UART2 pinmux */ + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + + /* UART5 pinmux */ + DEFAULT_PINMUX(SDMMC4_DAT0, UARTE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, UARTE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, UARTE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, UARTE, NORMAL, NORMAL, OUTPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* PowerI2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* SPI1 pinmux */ + DEFAULT_PINMUX(ULPI_CLK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT), + + /* SPI2 pinmux */ + DEFAULT_PINMUX(ULPI_DATA4, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, SPI2, NORMAL, NORMAL, INPUT), + + /* SPI4 pinmux */ + DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT), + + /* SPDIF pinmux */ + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + + /* DAP1 */ + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + + /* DAP2 */ + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + + /* DAP3 */ + DEFAULT_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT), + + /* NOR pinmux */ + DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD9, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD11, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD15, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_RST_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WAIT, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_WR_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_DIN, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_DOUT, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI1_MOSI, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_CS0_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MOSI, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPI2_MISO, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_FS, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_DIN, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_DOUT, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_SCLK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU2, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU3, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU6, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_TXD, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_CTS_N, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RTS_N, GMI, NORMAL, NORMAL, OUTPUT), + + + /* DISPLAY pinmux */ + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + + VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE), + + /* pin config for gpios */ + DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SAFE, NORMAL, NORMAL, INPUT), +}; + +int __init p1852_pinmux_init(void) +{ + tegra_pinmux_config_table(p1852_pinmux_common, + ARRAY_SIZE(p1852_pinmux_common)); + tegra_drive_pinmux_config_table(p1852_drive_pinmux, + ARRAY_SIZE(p1852_drive_pinmux)); + return 0; +} + +static struct gpio p1852_sku8_gpios[] = { + {TEGRA_GPIO_PW4, GPIOF_OUT_INIT_HIGH, "w4"}, + {TEGRA_GPIO_PEE2, GPIOF_OUT_INIT_HIGH, "ee2"}, + {TEGRA_GPIO_PZ4, GPIOF_OUT_INIT_HIGH, "z4"}, + {TEGRA_GPIO_PD2, GPIOF_OUT_INIT_HIGH, "d2"}, + {TEGRA_GPIO_PD1, GPIOF_OUT_INIT_HIGH, "d1"}, + {TEGRA_GPIO_PD0, GPIOF_OUT_INIT_HIGH, "d0"}, + {TEGRA_GPIO_PW2, GPIOF_IN, "therm_alert"}, + {TEGRA_GPIO_PK5, GPIOF_OUT_INIT_HIGH, "user1"}, + {TEGRA_GPIO_PX5, GPIOF_OUT_INIT_HIGH, "user2"}, + {TEGRA_GPIO_PX6, GPIOF_OUT_INIT_HIGH, "user3"}, + {TEGRA_GPIO_PX7, GPIOF_OUT_INIT_HIGH, "user4"}, +}; + +int __init p1852_gpio_init(void) +{ + int i, pin_count = 0; + struct gpio *gpios_info = NULL; + gpios_info = p1852_sku8_gpios; + pin_count = ARRAY_SIZE(p1852_sku8_gpios); + + gpio_request_array(gpios_info, pin_count); + for (i = 0; i < pin_count; i++) { + tegra_gpio_enable(gpios_info[i].gpio); + gpio_export(gpios_info[i].gpio, true); + } + return 0; +} diff --git a/arch/arm/mach-tegra/board-p1852-sdhci.c b/arch/arm/mach-tegra/board-p1852-sdhci.c new file mode 100644 index 000000000000..c1aa066ae1b0 --- /dev/null +++ b/arch/arm/mach-tegra/board-p1852-sdhci.c @@ -0,0 +1,79 @@ +/* + * arch/arm/mach-tegra/board-p1852-sdhci.c + * + * Copyright (C) 2010 Google, Inc. + * + * Copyright (C) 2012 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/resource.h> +#include <linux/platform_device.h> +#include <linux/wlan_plat.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/mmc/host.h> + +#include <asm/mach-types.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/sdhci.h> + +#include "gpio-names.h" +#include "board.h" +#include "board-p1852.h" +#include "devices.h" + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = { + .cd_gpio = TEGRA_GPIO_PV2, + .wp_gpio = TEGRA_GPIO_PD3, + .power_gpio = -1, + .is_8bit = false, +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .is_8bit = true, +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { + .cd_gpio = TEGRA_GPIO_PV3, + .wp_gpio = TEGRA_GPIO_PD4, + .power_gpio = -1, + .is_8bit = false, +}; + +static struct tegra_sdhci_platform_data tegra_sdhci_platform_data4 = { + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + .is_8bit = true, +}; + +int __init p1852_sdhci_init(void) +{ + tegra_sdhci_device1.dev.platform_data = &tegra_sdhci_platform_data1; + tegra_sdhci_device2.dev.platform_data = &tegra_sdhci_platform_data2; + tegra_sdhci_device3.dev.platform_data = &tegra_sdhci_platform_data3; + tegra_sdhci_device4.dev.platform_data = &tegra_sdhci_platform_data4; + + platform_device_register(&tegra_sdhci_device1); + platform_device_register(&tegra_sdhci_device2); + platform_device_register(&tegra_sdhci_device3); + platform_device_register(&tegra_sdhci_device4); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c new file mode 100644 index 000000000000..4b978da9f63d --- /dev/null +++ b/arch/arm/mach-tegra/board-p1852.c @@ -0,0 +1,393 @@ +/* + * arch/arm/mach-tegra/board-p1852.c + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/ctype.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> +#include <linux/i2c.h> +#include <linux/i2c/panjit_ts.h> +#include <linux/dma-mapping.h> +#include <linux/delay.h> +#include <linux/i2c-tegra.h> +#include <linux/gpio.h> +#include <linux/input.h> +#include <linux/platform_data/tegra_usb.h> +#include <linux/platform_data/tegra_nor.h> +#include <linux/spi/spi.h> +#include <linux/mtd/partitions.h> +#include <mach/clk.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/pinmux.h> +#include <mach/iomap.h> +#include <mach/io.h> +#include <mach/pci.h> +#include <mach/audio.h> +#include <asm/mach/flash.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/usb_phy.h> +#include <sound/wm8903.h> +#include <mach/tsensor.h> +#include "board.h" +#include "clock.h" +#include "board-p1852.h" +#include "devices.h" +#include "gpio-names.h" +#include "fuse.h" + +static struct tegra_utmip_config utmi_phy_config[] = { + [0] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 15, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, + [1] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 15, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, + [2] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 8, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, +}; + +static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = { + /* name parent rate enabled */ + { "pll_m", NULL, 0, true}, + { "hda", "pll_p", 108000000, false}, + { "hda2codec_2x", "pll_p", 48000000, false}, + { "pwm", "clk_32k", 32768, false}, + { "blink", "clk_32k", 32768, true}, + { "pll_a", NULL, 552960000, false}, + { "pll_a_out0", NULL, 12288000, false}, + { "d_audio", "pll_a_out0", 12288000, false}, + { "nor", "pll_p", 86500000, true}, + { "uarta", "pll_p", 480000000, true}, + { "uarte", "pll_p", 480000000, true}, + { "sdmmc2", "pll_p", 52000000, true}, + { "sbc1", "pll_m", 100000000, true}, + { "sbc2", "pll_m", 100000000, true}, + { "sbc3", "pll_m", 100000000, true}, + { "sbc4", "pll_m", 100000000, true}, + { "sbc5", "pll_m", 100000000, true}, + { "sbc6", "pll_m", 100000000, true}, + { "cpu_g", "cclk_g", 900000000, true}, + { "i2s0", "clk_m", 12288000, false}, + { "i2s1", "clk_m", 12288000, false}, + { "i2s2", "clk_m", 12288000, false}, + { "i2s3", "clk_m", 12288000, false}, + { "i2s4", "clk_m", 12288000, false}, + { "vi", "pll_p", 200000000, true}, + { "vi_sensor", "pll_p", 150000000, true}, + { "vde", "pll_c", 484000000, true}, + { "host1x", "pll_c", 300000000, true}, + { "mpe", "pll_c", 484000000, true}, + { "se", "pll_m", 650000000, true}, + { "i2c1", "pll_p", 3200000, true}, + { "i2c2", "pll_p", 3200000, true}, + { "i2c3", "pll_p", 3200000, true}, + { "i2c4", "pll_p", 3200000, true}, + { "i2c5", "pll_p", 3200000, true}, + { NULL, NULL, 0, 0}, +}; + +static struct tegra_i2c_platform_data p1852_i2c1_platform_data = { + .adapter_nr = 0, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data p1852_i2c2_platform_data = { + .adapter_nr = 1, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, + .is_clkon_always = true, +}; + +static struct tegra_i2c_platform_data p1852_i2c4_platform_data = { + .adapter_nr = 3, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_i2c_platform_data p1852_i2c5_platform_data = { + .adapter_nr = 4, + .bus_count = 1, + .bus_clk_rate = { 100000, 0 }, +}; + +static struct tegra_pci_platform_data p1852_pci_platform_data = { + .port_status[0] = 0, + .port_status[1] = 1, + .port_status[2] = 1, + .use_dock_detect = 0, + .gpio = 0, +}; + +static void p1852_pcie_init(void) +{ + tegra_pci_device.dev.platform_data = &p1852_pci_platform_data; + platform_device_register(&tegra_pci_device); +} + +static void p1852_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &p1852_i2c1_platform_data; + tegra_i2c_device2.dev.platform_data = &p1852_i2c2_platform_data; + tegra_i2c_device4.dev.platform_data = &p1852_i2c4_platform_data; + tegra_i2c_device5.dev.platform_data = &p1852_i2c5_platform_data; + + platform_device_register(&tegra_i2c_device5); + platform_device_register(&tegra_i2c_device4); + platform_device_register(&tegra_i2c_device2); + platform_device_register(&tegra_i2c_device1); +} + +static struct platform_device *p1852_uart_devices[] __initdata = { + &tegra_uarta_device, + &tegra_uartb_device, + &tegra_uarte_device, +}; +static struct clk *debug_uart_clk; + +static void __init uart_debug_init(void) +{ + /* Use skuinfo to decide debug uart */ + /* UARTB is the debug port. */ + pr_info("Selecting UARTB as the debug console\n"); + p1852_uart_devices[1] = &debug_uartb_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uartb"); +} + +static void __init p1852_uart_init(void) +{ + /* Register low speed only if it is selected */ + if (!is_tegra_debug_uartport_hs()) { + uart_debug_init(); + /* Clock enable for the debug channel */ + if (!IS_ERR_OR_NULL(debug_uart_clk)) { + pr_info("The debug console clock name is %s\n", + debug_uart_clk->name); + clk_enable(debug_uart_clk); + clk_set_rate(debug_uart_clk, 408000000); + } else { + pr_err("Not getting the clock %s for debug console\n", + debug_uart_clk->name); + } + } + + platform_add_devices(p1852_uart_devices, + ARRAY_SIZE(p1852_uart_devices)); +} + +#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV) +static struct spi_board_info tegra_spi_devices[] __initdata = { + { + .modalias = "spidev", + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", + .bus_num = 1, + .chip_select = 1, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", + .bus_num = 3, + .chip_select = 1, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, +}; + +static void __init p852_register_spidev(void) +{ + spi_register_board_info(tegra_spi_devices, + ARRAY_SIZE(tegra_spi_devices)); +} +#else +#define p852_register_spidev() do {} while (0) +#endif + + +static void p1852_spi_init(void) +{ + tegra_spi_device2.name = "spi_slave_tegra"; + platform_device_register(&tegra_spi_device1); + platform_device_register(&tegra_spi_device2); + platform_device_register(&tegra_spi_device4); + p852_register_spidev(); +} + +static struct platform_device *p1852_devices[] __initdata = { +#if defined(CONFIG_TEGRA_IOVMM_SMMU) + &tegra_smmu_device, +#endif +#if defined(CONFIG_TEGRA_AVP) + &tegra_avp_device, +#endif +}; + +static struct usb_phy_plat_data tegra_usb_phy_pdata[] = { + [0] = { + .instance = 0, + .vbus_gpio = -1, + .vbus_reg_supply = NULL, + }, + [1] = { + .instance = 1, + .vbus_gpio = -1, + }, + [2] = { + .instance = 2, + .vbus_gpio = -1, + .vbus_reg_supply = NULL, + }, +}; + +static struct tegra_ehci_platform_data tegra_ehci_pdata[] = { + [0] = { + .phy_config = &utmi_phy_config[0], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + }, + [1] = { + .phy_config = &utmi_phy_config[1], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + }, + [2] = { + .phy_config = &utmi_phy_config[2], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 1, + }, +}; + +static void p1852_usb_init(void) +{ + /* Need to parse sku info to decide host/device mode */ + tegra_usb_phy_init(tegra_usb_phy_pdata, + ARRAY_SIZE(tegra_usb_phy_pdata)); + + tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0]; + platform_device_register(&tegra_ehci1_device); + + tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1]; + platform_device_register(&tegra_ehci2_device); + + tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2]; + platform_device_register(&tegra_ehci3_device); + +} + +static struct tegra_nor_platform_data p1852_nor_data = { + .flash = { + .map_name = "cfi_probe", + .width = 2, + }, + .chip_parms = { + /* FIXME: Need to use characterized value */ + .timing_default = { + .timing0 = 0xA0400273, + .timing1 = 0x00030402, + }, + .timing_read = { + .timing0 = 0xA0400273, + .timing1 = 0x00030402, + }, + }, +}; + +static void p1852_nor_init(void) +{ + tegra_nor_device.resource[2].end = TEGRA_NOR_FLASH_BASE + SZ_64M - 1; + tegra_nor_device.dev.platform_data = &p1852_nor_data; + platform_device_register(&tegra_nor_device); +} + +static void __init tegra_p1852_init(void) +{ + tegra_clk_init_from_table(p1852_clk_init_table); + p1852_pinmux_init(); + p1852_i2c_init(); + p1852_gpio_init(); + p1852_uart_init(); + p1852_usb_init(); + p1852_sdhci_init(); + p1852_spi_init(); + platform_add_devices(p1852_devices, ARRAY_SIZE(p1852_devices)); + p1852_panel_init(); + p1852_nor_init(); + p1852_pcie_init(); +} + +static void __init tegra_p1852_reserve(void) +{ +#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) + tegra_reserve(0, SZ_8M, 0); +#else + tegra_reserve(SZ_128M, SZ_8M, 0); +#endif +} + +MACHINE_START(P1852, "p1852") + .boot_params = 0x80000100, + .init_irq = tegra_init_irq, + .init_early = tegra_init_early, + .init_machine = tegra_p1852_init, + .map_io = tegra_map_common_io, + .reserve = tegra_p1852_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-p1852.h b/arch/arm/mach-tegra/board-p1852.h new file mode 100644 index 000000000000..14339351ddcf --- /dev/null +++ b/arch/arm/mach-tegra/board-p1852.h @@ -0,0 +1,98 @@ +/* + * arch/arm/mach-tegra/board-p1852.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _MACH_TEGRA_BOARD_P1852_H +#define _MACH_TEGRA_BOARD_P1852_H + +#include <mach/gpio.h> +#include <mach/irqs.h> +#include <linux/mfd/tps6591x.h> + + +/* External peripheral act as gpio */ +/* TPS6591x GPIOs */ +#define TPS6591X_GPIO_BASE TEGRA_NR_GPIOS +#define TPS6591X_GPIO_GP0 (TPS6591X_GPIO_BASE + 0) +#define TPS6591X_GPIO_GP1 (TPS6591X_GPIO_BASE + 1) +#define TPS6591X_GPIO_GP2 (TPS6591X_GPIO_BASE + 2) +#define TPS6591X_GPIO_GP3 (TPS6591X_GPIO_BASE + 3) +#define TPS6591X_GPIO_GP4 (TPS6591X_GPIO_BASE + 4) +#define TPS6591X_GPIO_GP5 (TPS6591X_GPIO_BASE + 5) +#define TPS6591X_GPIO_GP6 (TPS6591X_GPIO_BASE + 6) +#define TPS6591X_GPIO_GP7 (TPS6591X_GPIO_BASE + 7) +#define TPS6591X_GPIO_GP8 (TPS6591X_GPIO_BASE + 8) +#define TPS6591X_GPIO_END TPS6591X_GPIO_GP8 + +/* CAM_TCA6416 GPIOs */ +#define CAM_TCA6416_GPIO_BASE (TPS6591X_GPIO_END + 1) +#define CAM1_PWR_DN_GPIO (CAM_TCA6416_GPIO_BASE + 0) +#define CAM1_RST_L_GPIO (CAM_TCA6416_GPIO_BASE + 1) +#define CAM1_AF_PWR_DN_L_GPIO (CAM_TCA6416_GPIO_BASE + 2) +#define CAM1_LDO_SHUTDN_L_GPIO (CAM_TCA6416_GPIO_BASE + 3) +#define CAM2_PWR_DN_GPIO (CAM_TCA6416_GPIO_BASE + 4) +#define CAM2_RST_L_GPIO (CAM_TCA6416_GPIO_BASE + 5) +#define CAM2_AF_PWR_DN_L_GPIO (CAM_TCA6416_GPIO_BASE + 6) +#define CAM2_LDO_SHUTDN_L_GPIO (CAM_TCA6416_GPIO_BASE + 7) +#define CAM_FRONT_PWR_DN_GPIO (CAM_TCA6416_GPIO_BASE + 8) +#define CAM_FRONT_RST_L_GPIO (CAM_TCA6416_GPIO_BASE + 9) +#define CAM_FRONT_AF_PWR_DN_L_GPIO (CAM_TCA6416_GPIO_BASE + 10) +#define CAM_FRONT_LDO_SHUTDN_L_GPIO (CAM_TCA6416_GPIO_BASE + 11) +#define CAM_FRONT_LED_EXP (CAM_TCA6416_GPIO_BASE + 12) +#define CAM_SNN_LED_REAR_EXP (CAM_TCA6416_GPIO_BASE + 13) +/* PIN 19 NOT USED and is reserved */ +#define CAM_NOT_USED (CAM_TCA6416_GPIO_BASE + 14) +#define CAM_I2C_MUX_RST_EXP (CAM_TCA6416_GPIO_BASE + 15) +#define CAM_TCA6416_GPIO_END CAM_I2C_MUX_RST_EXP + +/* WM8903 gpios */ +#define WM8903_GPIO_BASE (CAM_TCA6416_GPIO_END + 1) +#define WM8903_GP1 (WM8903_GPIO_BASE + 0) +#define WM8903_GP2 (WM8903_GPIO_BASE + 1) +#define WM8903_GP3 (WM8903_GPIO_BASE + 2) +#define WM8903_GP4 (WM8903_GPIO_BASE + 3) +#define WM8903_GP5 (WM8903_GPIO_BASE + 4) +#define WM8903_GPIO_END WM8903_GP5 + +/* CAMERA RELATED GPIOs on p1852 */ +#define OV5650_RESETN_GPIO TEGRA_GPIO_PBB0 +#define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 +#define CAM2_POWER_DWN_GPIO TEGRA_GPIO_PBB6 +#define CAM3_POWER_DWN_GPIO TEGRA_GPIO_PBB7 +#define CAMERA_CSI_CAM_SEL_GPIO TEGRA_GPIO_PBB4 +#define CAMERA_CSI_MUX_SEL_GPIO TEGRA_GPIO_PCC1 +#define CAM1_LDO_EN_GPIO TEGRA_GPIO_PR6 +#define CAM2_LDO_EN_GPIO TEGRA_GPIO_PR7 +#define CAM3_LDO_EN_GPIO TEGRA_GPIO_PS0 + + +#define AC_PRESENT_GPIO TPS6591X_GPIO_GP4 +/*****************Interrupt tables ******************/ +/* External peripheral act as interrupt controller */ +/* TPS6591x IRQs */ +#define TPS6591X_IRQ_BASE TEGRA_NR_IRQS +#define TPS6591X_IRQ_END (TPS6591X_IRQ_BASE + 18) + +#define AC_PRESENT_INT (TPS6591X_INT_GPIO4 + TPS6591X_IRQ_BASE) + +int p1852_sdhci_init(void); +int p1852_pinmux_init(void); +int p1852_panel_init(void); +int p1852_gpio_init(void); +int p1852_pins_state_init(void); + +#endif |