diff options
| author | Gary King <gking@nvidia.com> | 2010-05-27 21:37:04 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-05-27 21:41:28 -0700 |
| commit | 732dda02eddda241d68f043a331d4c38c193ed63 (patch) | |
| tree | 039bc144e3484c59176444a4d9883be4aa7707ce /arch | |
| parent | 9847ff5ac680ce6b1c10425c8893b744c8cfeb15 (diff) | |
[ARM/tegra] pl310: re-enable prefetching
only certain prefetch offest values in Tegra 2's PL310 cross 4K boundaries.
the value originally programmed (reverted in commit 61ad8dcf), 8, was
one of the broken values. a prefetch offset of 7 has nearly the same
performance as 8, and won't cross 4K boundaries.
Change-Id: Ie8b4f6aa419e47b3ec553faeb8e4e2d95c2b37a9
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 96d7091dea43..33eb91e8c2ab 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -47,8 +47,9 @@ void __init tegra_init_cache(void) writel(0x331, p + L2X0_TAG_LATENCY_CTRL); writel(0x441, p + L2X0_DATA_LATENCY_CTRL); + writel(7, p + L2X0_PREFETCH_OFFSET); - l2x0_init(p, 0x6C080001, 0x8200c3fe); + l2x0_init(p, 0x7C080001, 0x8200c3fe); #endif } |