diff options
author | Troy Kisky <troy.kisky@boundarydevices.com> | 2012-07-03 16:45:55 -0700 |
---|---|---|
committer | Eric Nelson <eric.nelson@boundarydevices.com> | 2012-08-31 17:57:08 -0700 |
commit | 6e53ee58dc9eb2a90edca6aee26c3cfbb905ae4a (patch) | |
tree | ef2d4091f993a30ed6e4d3ac87bcbe63bf9766e8 /arch | |
parent | 3867e7a16b495ef81734f7982af44a4848bb804d (diff) |
sabrelite: allow gigabit, 0 tx delay, set phy irq
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx6/board-mx6q_sabrelite.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c index eff81acb3208..c1eebcadd81c 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c +++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c @@ -92,6 +92,7 @@ #define MX6Q_SABRELITE_VOL_DOWN_KEY IMX_GPIO_NR(4, 5) #define MX6Q_SABRELITE_CSI0_RST IMX_GPIO_NR(1, 8) #define MX6Q_SABRELITE_CSI0_PWN IMX_GPIO_NR(1, 6) +#define MX6Q_SABRELITE_ENET_PHY_INT IMX_GPIO_NR(1, 28) #define MX6Q_SABRELITE_SD3_WP_PADCFG (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \ @@ -449,13 +450,17 @@ static inline void mx6q_sabrelite_init_uart(void) static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev) { - /* prefer master mode, disable 1000 Base-T capable */ - phy_write(phydev, 0x9, 0x1c00); + /* prefer master mode */ + phy_write(phydev, 0x9, 0x1f00); /* min rx data delay */ phy_write(phydev, 0x0b, 0x8105); phy_write(phydev, 0x0c, 0x0000); + /* min tx data delay */ + phy_write(phydev, 0x0b, 0x8106); + phy_write(phydev, 0x0c, 0x0000); + /* max rx/tx clock delay, min rx/tx control delay */ phy_write(phydev, 0x0b, 0x8104); phy_write(phydev, 0x0c, 0xf0f0); @@ -467,6 +472,7 @@ static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev) static struct fec_platform_data fec_data __initdata = { .init = mx6q_sabrelite_fec_phy_init, .phy = PHY_INTERFACE_MODE_RGMII, + .phy_irq = gpio_to_irq(MX6Q_SABRELITE_ENET_PHY_INT) }; static int mx6q_sabrelite_spi_cs[] = { |