summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-07-25 17:30:31 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-07-25 17:30:31 +0200
commit9af6146a4403e714c898690619d1f841bb1149d0 (patch)
tree1c3f05f4e3377984758af094fb017f6782f46396 /arch
parentb562b12b12ba303d5ceca17b347d8c506e18f7f4 (diff)
tegra: colibri_t20: decrease NAND clock
Looks like the older modules prior to V1.2 using Micron MT29F8G08ABCBB NAND flash parts have some timing issue. Decreasing the NAND flash controller clock from 144 back to 108 MHz seems to make it work again. Further investigation pending (e.g. explicitly setting timing mode 4).
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/board-colibri_t20.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20.c b/arch/arm/mach-tegra/board-colibri_t20.c
index 3db37cd2ef09..4771178bb2bf 100644
--- a/arch/arm/mach-tegra/board-colibri_t20.c
+++ b/arch/arm/mach-tegra/board-colibri_t20.c
@@ -123,7 +123,7 @@ static __initdata struct tegra_clk_init_table colibri_t20_clk_init_table[] = {
// {"avp.sclk", "virt_sclk", 250000000, false},
//dynamic
{"apbdma", "pclk", 36000000, false},
- {"ndflash", "pll_p", 144000000, false},
+ {"ndflash", "pll_p", 108000000, false},
//[ 2.284308] kernel BUG at drivers/spi/spi-tegra.c:254!
//[ 2.289454] Unable to handle kernel NULL pointer dereference at virtual address 00000000