diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-07-11 17:02:54 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-07-18 11:34:40 -0500 |
| commit | d9778ca18a4b8b34ea7e5891b7cacafed8621e98 (patch) | |
| tree | e02c43f791f79774a866fc6137807516271a4b1a /arch | |
| parent | 718ad7dc73744af2dc6f372ef0e4ebd507db6ed2 (diff) | |
ENGR00153261: MX50- Disable Auto clock gating of APLL.
The HW automatically tries to clock gate APLL is all the PFDs
are disabled, resulting in a possible race condition since
the SW also tries to disable the APLL.
Fix by clearing the PFD disable MASK bits in APLL.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index 94bb100b7089..4226822bd95a 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -3464,6 +3464,10 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long __raw_writel(MXC_ANADIG_REF_SELFBIAS_OFF, apll_base + MXC_ANADIG_MISC_SET); + /* Make sure to disable APLL auto-disable feature. */ + __raw_writel((MXC_ANADIG_PFD_DIS_MASK << MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_CLR); + clk_enable(&elcdif_pix_clk); clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk); clk_disable(&elcdif_pix_clk); |