diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-06-21 12:54:09 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-06-22 10:04:55 -0500 |
| commit | 3e340165172abdafaeab229de2d445b90b189674 (patch) | |
| tree | c23a9b3ca88544a09220106c97ff3961d525f169 /arch | |
| parent | 5fb3475cb65fd956a8433451951b081de758f035 (diff) | |
ENGR00151891: MX50-Fix bug in exit from LPAPM mode.
When exiting from LPAPM mode, ARM clock is run at 266.67MHZ for
a few instructions while the voltage is still at 0.85V.
Fix this issue by setting the ARM-PODF divider before
switching the parent.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx5/bus_freq.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index a4cd0d982b93..03caf7b92aff 100644 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -497,9 +497,12 @@ void exit_lpapm_mode_mx50(int high_bus_freq) __raw_writel(0x02, MXC_CCM_CACRR); clk_set_rate(pll1, cpu_wp_tbl[0].pll_rate); - clk_set_parent(pll1_sw_clk, pll1); - /* Set the divider to ARM_PODF to 5. */ + + /* Set the divider to ARM_PODF to 5 before + * switching the parent. + */ __raw_writel(0x4, MXC_CCM_CACRR); + clk_set_parent(pll1_sw_clk, pll1); } if (!completion_done(&voltage_change_cmpl)) |