diff options
| author | Dong Aisheng <b29396@freescale.com> | 2011-05-10 13:55:08 +0800 |
|---|---|---|
| committer | Alan Tull <alan.tull@freescale.com> | 2011-06-03 16:41:57 -0500 |
| commit | 83bb28a1f0ea6e0b5936da0846aac14d786f5171 (patch) | |
| tree | 7a2bcd18af505737389f51a4bbcae4de4f74d83e /arch | |
| parent | a5441e48294e9b42e7db5b5de6f4867cbc7b0b78 (diff) | |
ENGR00143179-3 mx50 clock: add digctl clk
It's required for control digctl register and enabling usdhc mode
needs to write this register.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index 3158cf8843a3..0fbd6c33480e 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -2021,6 +2021,14 @@ static struct clk usb_phy_clk[] = { } }; +static struct clk digctl_clk = { + .id = 0, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .disable = _clk_disable, +}; + static struct clk esdhc_dep_clks = { .parent = &spba_clk, .secondary = &ddr_clk, @@ -3166,6 +3174,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxsdhci.1", NULL, esdhc2_clk[0]), _REGISTER_CLOCK("mxsdhci.2", NULL, esdhc3_clk[0]), _REGISTER_CLOCK("mxsdhci.3", NULL, esdhc4_clk[0]), + _REGISTER_CLOCK(NULL, "digctl_clk", digctl_clk), _REGISTER_CLOCK(NULL, "ddr_clk", ddr_clk), _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk), _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), @@ -3283,8 +3292,6 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long 2 << MXC_CCM_CCGRx_CG14_OFFSET | 3 << MXC_CCM_CCGRx_CG15_OFFSET, MXC_CCM_CCGR6); - __raw_writel(0, MXC_CCM_CCGR7); - external_low_reference = ckil; external_high_reference = ckih1; oscillator_reference = osc; |