diff options
| author | Chris Johnson <cwj@nvidia.com> | 2012-02-14 17:27:08 -0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-05-21 18:46:54 -0700 |
| commit | 52effd517ca3520d10311be1885f860414928e6f (patch) | |
| tree | 23358ce80f7fafec5ca8779320fddf25b56aa7c3 /arch | |
| parent | acb115ca36385e4ef28a53502c9113c51695597e (diff) | |
ARM: tegra: define/enable ARCH_HAS_SUSPEND_PAGETABLE
For Tegra, the CPU suspend code path installs its own 1:1 pagetable
setup once at init time. This pagetable is used by all CPUs doing
suspend/resume.
We want to use the common ARM code for CPU suspend/resume, but don't
want the MMU reenable code to patch the current pagetable as it's
shared (and could cause problems if the pagetable loads/stores were
were interleaved).
The installed pagetable already covers the cpu_resume_turn_mmu_on
VA, so we're able to just use the existing pagetable. This sets up
the CONFIG option to skip this part of the MMU reenable.
Bug 929856
Change-Id: Ibbac258122df6def7f7a2d511778a6f11d474938
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/92350
Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com>
Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Ahung Cheng <ahcheng@nvidia.com>
Tested-by: Ahung Cheng <ahcheng@nvidia.com>
Reviewed-on: http://git-master/r/103205
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/kernel/sleep.S | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 2 |
3 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fcbd87b17507..5132b50295eb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1696,6 +1696,14 @@ config HW_PERF_EVENTS Enable hardware performance counter support for perf events. If disabled, perf events will use software events only. +config ARCH_HAS_SUSPEND_PAGETABLE + bool + help + This option indicates the platform architecture installs its own + 1:1 pagetable during CPU suspend/resume codepaths. This means the + patching of the pagetable as part of reenabling the MMU isn't + needed in the ARM common CPU resume codepath. If in doubt, say N. + source "mm/Kconfig" config FORCE_MAX_ZONEORDER diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index e87f5f243012..714664b2b2ee 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -72,12 +72,14 @@ ENDPROC(cpu_suspend_abort) * r3 = L1 section flags */ ENTRY(cpu_resume_mmu) +#ifndef CONFIG_ARCH_HAS_SUSPEND_PAGETABLE adr r4, cpu_resume_turn_mmu_on mov r4, r4, lsr #20 orr r3, r3, r4, lsl #20 ldr r5, [r2, r4, lsl #2] @ save old mapping str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code sub r2, r2, r1 +#endif ldr r3, =cpu_resume_after_mmu bic r1, r0, #CR_C @ ensure D-cache is disabled b cpu_resume_turn_mmu_on @@ -92,7 +94,9 @@ cpu_resume_turn_mmu_on: mov pc, r3 @ jump to virtual address ENDPROC(cpu_resume_turn_mmu_on) cpu_resume_after_mmu: +#ifndef CONFIG_ARCH_HAS_SUSPEND_PAGETABLE str r5, [r2, r4, lsl #2] @ restore old mapping +#endif mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache mov r0, #0 @ return zero on success ldmfd sp!, {r4 - r11, pc} diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 8ee5810e38ab..1aa448c44fcd 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -22,6 +22,7 @@ config ARCH_TEGRA_2x_SOC select PCI_MSI if TEGRA_PCI select CPA select ARM_ERRATA_716044 + select ARCH_HAS_SUSPEND_PAGETABLE help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -47,6 +48,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_754322 select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS select CPA + select ARCH_HAS_SUSPEND_PAGETABLE help Support for NVIDIA Tegra 3 family of SoCs, based upon the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |