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authorHiro Sugawara <hsugawara@nvidia.com>2012-05-10 14:57:50 -0700
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-05-18 05:13:56 -0700
commit699f36d343c7fbc7e3337f11e7a9814740c7f104 (patch)
treefbd5d5edf9f0c8da325275f21f74bfd52b0b967e /arch
parent805ec6fc5c6c5ebceaac3ab3a963e7cf9c772eea (diff)
ARM: tegra: smmu: Use non-secure register for sync-read
Bug 973463 Change-Id: Ia2e42232e6f10d12387b2bc3bbee1f996e7aea9d Signed-off-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-on: http://git-master/r/101837 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/iovmm-smmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/iovmm-smmu.c b/arch/arm/mach-tegra/iovmm-smmu.c
index 7e815e2fc7b2..6cdeb744a04c 100644
--- a/arch/arm/mach-tegra/iovmm-smmu.c
+++ b/arch/arm/mach-tegra/iovmm-smmu.c
@@ -339,7 +339,7 @@ struct smmu_device {
* must have these read-back to ensure the APB/AHB bus transaction is
* complete before initiating activity on the PPSB block.
*/
-#define FLUSH_SMMU_REGS(smmu) (void)readl((smmu)->regs + MC_SMMU_CONFIG_0)
+#define FLUSH_SMMU_REGS(smmu) (void)readl((smmu)->regs + MC_SMMU_PTB_DATA_0)
/*
* Flush all TLB entries and all PTC entries