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authorsreenivasulu velpula <svelpula@nvidia.com>2014-07-18 12:41:29 +0530
committerWinnie Hsu <whsu@nvidia.com>2014-10-27 12:51:51 -0700
commitc88d2d2b83e54540bd53f2e109661e9a19927ef0 (patch)
tree4e67216b9fa23a4d2aaf0e57c682f963db90b70e /arch
parentaaec98b4fddfc6780705e30bb885f1d89be2f0a4 (diff)
arm: tegra: Modify TEGRA_USE_DFLL_RANGE
Change TEGRA_USE_DFLL_RANGE to add one more range value "3" - DFLL usage is controlled by thermal cooling device Bug 1563635 Change-Id: Ib8443e0f9574632e0e2370618175fd40132a4488 Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com> Reviewed-on: http://git-master/r/439760 (cherry picked from commit 930c190253d3253a632d8a3c0e12c08a2e490eef) Reviewed-on: http://git-master/r/559388 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/Kconfig4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 71ecf93a1a4b..c886ee8f8eac 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -719,7 +719,8 @@ config TEGRA_IO_DPD
config TEGRA_USE_DFLL_RANGE
int "Default CPU DFLL operating range"
depends on ARCH_TEGRA_HAS_CL_DVFS
- range 0 2
+ range 0 3
+ default "0" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_21x_SOC
default "1" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_13x_SOC
default "2" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_11x_SOC
default "1"
@@ -730,6 +731,7 @@ config TEGRA_USE_DFLL_RANGE
"1" - DFLL is used as a source for all CPU rates
"2" - DFLL is used only for high rates above crossover with
PLL dvfs curve
+ "3" - DFLL usage is controlled by thermal cooling device
config REGULATOR_TEGRA_DFLL_BYPASS
bool "Use dfll bypass regulator"