diff options
| author | Sean Wang <sean.wang@mediatek.com> | 2017-04-26 17:25:59 +0800 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2017-05-15 10:47:08 +0200 |
| commit | 687976ae99823b76547f16dd3e767006244ec402 (patch) | |
| tree | 50e8788c5d53fd9c45c3b56fd62c2a91c14d9b3f /arch | |
| parent | ffdbc3cfc504245a883ed0ef49bfd3a913caf4b0 (diff) | |
arm: dts: mt7623: add ethernet nodes to the mt7623.dtsi file
Add ethernet nodes to the mt7623.dtsi file.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/mt7623.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 27823307d71e..4d3011256470 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -483,4 +483,24 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt2701-eth", "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <ðsys CLK_ETHSYS_ESW>, + <ðsys CLK_ETHSYS_GP1>, + <ðsys CLK_ETHSYS_GP2>, + <&apmixedsys CLK_APMIXED_TRGPLL>; + clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + mediatek,ethsys = <ðsys>; + mediatek,pctl = <&syscfg_pctl_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; |