arm64: dts: imx8: split adma ss into dma and audio ss

amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

6 files changed, 796 insertions, 774 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
index 9393e9bc5b94..841758bd2c8c 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
@@ -4,759 +4,5 @@
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
 
-#include <dt-bindings/firmware/imx/rsrc.h>
-
-adma_subsys: bus@59000000 {
-	compatible = "simple-bus";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges = <0x59000000 0x0 0x59000000 0x2000000>;
-
-	dma_ipg_clk: clock-dma-ipg {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <120000000>;
-		clock-output-names = "dma_ipg_clk";
-	};
-
-	edma0: dma-controller@591F0000 {
-		compatible = "fsl,imx8qm-edma";
-		reg = <0x59200000 0x10000>, /* asrc0 */
-			<0x59210000 0x10000>,
-			<0x59220000 0x10000>,
-			<0x59230000 0x10000>,
-			<0x59240000 0x10000>,
-			<0x59250000 0x10000>,
-			<0x59260000 0x10000>, /* esai0 rx */
-			<0x59270000 0x10000>, /* esai0 tx */
-			<0x59280000 0x10000>, /* spdif0 rx */
-			<0x59290000 0x10000>, /* spdif0 tx */
-			<0x592c0000 0x10000>, /* sai0 rx */
-			<0x592d0000 0x10000>, /* sai0 tx */
-			<0x592e0000 0x10000>, /* sai1 rx */
-			<0x592f0000 0x10000>, /* sai1 tx */
-			<0x59350000 0x10000>,
-			<0x59370000 0x10000>;
-		#dma-cells = <3>;
-		shared-interrupt;
-		dma-channels = <16>;
-		interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
-				<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
-				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
-				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
-				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
-				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
-				"edma0-chan2-rx", "edma0-chan3-tx",
-				"edma0-chan4-tx", "edma0-chan5-tx",
-				"edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
-				"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
-				"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
-				"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
-				"edma0-chan21-tx",		/* gpt5 */
-				"edma0-chan23-rx";		/* gpt7 */
-		status = "okay";
-	};
-
-	edma1: dma-controller@599F0000 {
-		compatible = "fsl,imx8qm-edma";
-		reg = <0x59A00000 0x10000>, /* asrc1 */
-			<0x59A10000 0x10000>,
-			<0x59A20000 0x10000>,
-			<0x59A30000 0x10000>,
-			<0x59A40000 0x10000>,
-			<0x59A50000 0x10000>,
-			<0x59A80000 0x10000>, /* sai4 rx */
-			<0x59A90000 0x10000>, /* sai4 tx */
-			<0x59AA0000 0x10000>; /* sai5 tx */
-		#dma-cells = <3>;
-		shared-interrupt;
-		dma-channels = <9>;
-		interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
-				<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
-				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
-		interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
-				"edma1-chan2-rx", "edma1-chan3-tx",
-				"edma1-chan4-tx", "edma1-chan5-tx",
-				"edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
-				"edma1-chan10-tx";                 /* sai5 */
-		status = "okay";
-	};
-
-	edma2: dma-controller@5a1f0000 {
-		compatible = "fsl,imx8qm-edma";
-		reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
-		      <0x5a290000 0x10000>, /* channel9 UART0 tx */
-		      <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
-		      <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
-		      <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
-		      <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
-		      <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
-		      <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
-		#dma-cells = <3>;
-		dma-channels = <8>;
-		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
-				  "edma2-chan10-rx", "edma2-chan11-tx",
-				  "edma2-chan12-rx", "edma2-chan13-tx",
-				  "edma2-chan14-rx", "edma2-chan15-tx";
-		status = "disabled";
-	};
-
-	adma_lpspi0: spi@5a000000 {
-		compatible = "fsl,imx7ulp-spi";
-		reg = <0x5a000000 0x10000>;
-		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPI0_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_SPI0_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX_ADMA_SPI0_CLK>;
-		assigned-clock-rates = <20000000>;
-		power-domains = <&pd IMX_SC_R_SPI_0>;
-		status = "disabled";
-	};
-
-	adma_lpspi2: spi@5a020000 {
-		compatible = "fsl,imx7ulp-spi";
-		reg = <0x5a020000 0x10000>;
-		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPI2_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_SPI2_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX_ADMA_SPI2_CLK>;
-		assigned-clock-rates = <20000000>;
-		power-domains = <&pd IMX_SC_R_SPI_2>;
-		status = "disabled";
-	};
-
-	adma_lpuart0: serial@5a060000 {
-		reg = <0x5a060000 0x1000>;
-		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>;
-		clock-names = "ipg", "baud";
-		assigned-clocks = <&clk IMX_ADMA_UART0_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd IMX_SC_R_UART_0>;
-		status = "disabled";
-	};
-
-	adma_lpuart1: serial@5a070000 {
-		reg = <0x5a070000 0x1000>;
-		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>;
-		clock-names = "ipg", "baud";
-		assigned-clocks = <&clk IMX_ADMA_UART1_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd IMX_SC_R_UART_1>,
-				<&pd IMX_SC_R_DMA_2_CH10>,
-				<&pd IMX_SC_R_DMA_2_CH11>;
-		power-domain-names = "uart", "rxdma", "txdma";
-		dma-names = "tx","rx";
-		dmas = <&edma2 11 0 0>,
-			<&edma2 10 0 1>;
-		status = "disabled";
-	};
-
-	adma_lpuart2: serial@5a080000 {
-		reg = <0x5a080000 0x1000>;
-		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>;
-		clock-names = "ipg", "baud";
-		assigned-clocks = <&clk IMX_ADMA_UART2_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd IMX_SC_R_UART_2>,
-				<&pd IMX_SC_R_DMA_2_CH12>,
-				<&pd IMX_SC_R_DMA_2_CH13>;
-		power-domain-names = "uart", "rxdma", "txdma";
-		dma-names = "tx","rx";
-		dmas = <&edma2 13 0 0>,
-			<&edma2 12 0 1>;
-		status = "disabled";
-	};
-
-	adma_lpuart3: serial@5a090000 {
-		reg = <0x5a090000 0x1000>;
-		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>;
-		clock-names = "ipg", "baud";
-		assigned-clocks = <&clk IMX_ADMA_UART3_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd IMX_SC_R_UART_3>,
-				<&pd IMX_SC_R_DMA_2_CH14>,
-				<&pd IMX_SC_R_DMA_2_CH15>;
-		power-domain-names = "uart", "rxdma", "txdma";
-		dma-names = "tx","rx";
-		dmas = <&edma2 15 0 0>,
-			<&edma2 14 0 1>;
-		status = "disabled";
-	};
-
-	uart0_lpcg: clock-controller@5a460000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5a460000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "uart0_lpcg_baud_clk",
-				     "uart0_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_UART_0>;
-	};
-
-	uart1_lpcg: clock-controller@5a470000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5a470000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "uart1_lpcg_baud_clk",
-				     "uart1_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_UART_1>;
-	};
-
-	uart2_lpcg: clock-controller@5a480000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5a480000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "uart2_lpcg_baud_clk",
-				     "uart2_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_UART_2>;
-	};
-
-	uart3_lpcg: clock-controller@5a490000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5a490000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "uart3_lpcg_baud_clk",
-				     "uart3_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_UART_3>;
-	};
-
-	adma_i2c0: i2c@5a800000 {
-		reg = <0x5a800000 0x4000>;
-		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&i2c0_lpcg 0>;
-		clock-names = "per";
-		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd IMX_SC_R_I2C_0>;
-		status = "disabled";
-	};
-
-	adma_i2c1: i2c@5a810000 {
-		reg = <0x5a810000 0x4000>;
-		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&i2c1_lpcg 0>;
-		clock-names = "per";
-		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd IMX_SC_R_I2C_1>;
-		status = "disabled";
-	};
-
-	adma_i2c2: i2c@5a820000 {
-		reg = <0x5a820000 0x4000>;
-		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&i2c2_lpcg 0>;
-		clock-names = "per";
-		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd IMX_SC_R_I2C_2>;
-		status = "disabled";
-	};
-
-	adma_i2c3: i2c@5a830000 {
-		reg = <0x5a830000 0x4000>;
-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&i2c3_lpcg 0>;
-		clock-names = "per";
-		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd IMX_SC_R_I2C_3>;
-		status = "disabled";
-	};
-
-	flexcan1: can@5a8d0000 {
-		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
-		reg = <0x5a8d0000 0x10000>;
-		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
-		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
-		assigned-clock-rates = <40000000>;
-		power-domains = <&pd IMX_SC_R_CAN_0>;
-		/* SLSlice[4] */
-		fsl,clk-source= <0>;
-		status = "disabled";
-	};
-
-	flexcan2: can@5a8e0000 {
-		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
-		reg = <0x5a8e0000 0x10000>;
-		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
-		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
-		assigned-clock-rates = <40000000>;
-		/* CAN1 shares CAN0's clock, to enable CAN0's clock it has
-		 * to be powered on, so CAN1 depends on CAN0's power domain.
-		 */
-		power-domains = <&pd IMX_SC_R_CAN_1>, <&pd IMX_SC_R_CAN_0>;
-		power-domain-names = "can_pd", "can_aux_pd";
-		/* SLSlice[4] */
-		fsl,clk-source = <0>;
-		status = "disabled";
-	};
-
-	flexcan3: can@5a8f0000 {
-		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
-		reg = <0x5a8f0000 0x10000>;
-		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
-		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
-		assigned-clock-rates = <40000000>;
-		/* CAN2 shares CAN0's clock, to enable CAN0's clock it has
-		 * to be powered on, so CAN2 depends on CAN0's power domain.
-		 */
-		power-domains = <&pd IMX_SC_R_CAN_2>, <&pd IMX_SC_R_CAN_0>;
-		power-domain-names = "can_pd", "can_aux_pd";
-		/* SLSlice[4] */
-		fsl,clk-source = <0>;
-		status = "disabled";
-	};
-
-	adma_acm: acm@59e00000 {
-		compatible = "nxp,imx8qxp-acm";
-		reg = <0x59e00000 0x1D0000>;
-		#clock-cells = <1>;
-		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_MCLK_OUT_0>,
-				<&pd IMX_SC_R_MCLK_OUT_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>,
-				<&pd IMX_SC_R_ASRC_0>,
-				<&pd IMX_SC_R_ASRC_1>,
-				<&pd IMX_SC_R_ESAI_0>,
-				<&pd IMX_SC_R_SAI_0>,
-				<&pd IMX_SC_R_SAI_1>,
-				<&pd IMX_SC_R_SAI_2>,
-				<&pd IMX_SC_R_SAI_3>,
-				<&pd IMX_SC_R_SAI_4>,
-				<&pd IMX_SC_R_SAI_5>,
-				<&pd IMX_SC_R_SPDIF_0>,
-				<&pd IMX_SC_R_MQS_0>;
-	};
-
-	adma_dsp: dsp@596e8000 {
-		compatible = "fsl,imx8qxp-dsp";
-		reg = <0x596e8000 0x88000>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
-			 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
-		clock-names = "ipg", "ocram", "core";
-		fsl,dsp-firmware = "imx/dsp/hifi4.bin";
-		power-domains = <&pd IMX_SC_R_MU_13A>,
-				<&pd IMX_SC_R_MU_13B>,
-				<&pd IMX_SC_R_DSP>,
-				<&pd IMX_SC_R_DSP_RAM>;
-		reserved-region = <&dsp_reserved>;
-		status = "disabled";
-	};
-
-	adma_asrc0: asrc@59000000 {
-		compatible = "fsl,imx8qm-asrc0";
-		reg = <0x59000000 0x10000>;
-		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
-			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
-			<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
-			<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "ipg", "mem",
-			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
-			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
-			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
-			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
-			"spba";
-		dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
-			<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
-		dma-names = "rxa", "rxb", "rxc",
-				"txa", "txb", "txc";
-		fsl,asrc-rate  = <8000>;
-		fsl,asrc-width = <16>;
-		power-domains = <&pd IMX_SC_R_ASRC_0>,
-				<&pd IMX_SC_R_DMA_0_CH0>,
-				<&pd IMX_SC_R_DMA_0_CH1>,
-				<&pd IMX_SC_R_DMA_0_CH2>,
-				<&pd IMX_SC_R_DMA_0_CH3>,
-				<&pd IMX_SC_R_DMA_0_CH4>,
-				<&pd IMX_SC_R_DMA_0_CH5>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-        };
-
-	adma_esai0: esai@59010000 {
-		compatible = "fsl,imx8qm-esai";
-		reg = <0x59010000 0x10000>;
-		interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
-			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK>,
-			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "core", "extal", "fsys", "spba";
-		dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
-		dma-names = "rx", "tx";
-		power-domains = <&pd IMX_SC_R_ESAI_0>,
-				<&pd IMX_SC_R_DMA_0_CH6>,
-				<&pd IMX_SC_R_DMA_0_CH7>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_spdif0: spdif@59020000 {
-		compatible = "fsl,imx8qm-spdif";
-		reg = <0x59020000 0x10000>;
-		interrupts =  <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
-			<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPDIF_0_GCLKW>, /* core */
-			<&clk IMX_CLK_DUMMY>, /* rxtx0 */
-			<&adma_lpcg IMX_ADMA_LPCG_SPDIF_0_TX_CLK>, /* rxtx1 */
-			<&clk IMX_CLK_DUMMY>, /* rxtx2 */
-			<&clk IMX_CLK_DUMMY>, /* rxtx3 */
-			<&clk IMX_CLK_DUMMY>, /* rxtx4 */
-			<&clk IMX_ADMA_IPG_CLK_ROOT>, /* rxtx5 */
-			<&clk IMX_CLK_DUMMY>, /* rxtx6 */
-			<&clk IMX_CLK_DUMMY>, /* rxtx7 */
-			<&clk IMX_CLK_DUMMY>; /* spba */
-		clock-names = "core", "rxtx0",
-				"rxtx1", "rxtx2",
-				"rxtx3", "rxtx4",
-				"rxtx5", "rxtx6",
-				"rxtx7", "spba";
-		dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
-		dma-names = "rx", "tx";
-		power-domains = <&pd IMX_SC_R_SPDIF_0>,
-				<&pd IMX_SC_R_DMA_0_CH8>,
-				<&pd IMX_SC_R_DMA_0_CH9>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_sai0: sai@59040000 {
-		compatible = "fsl,imx8qm-sai";
-		reg = <0x59040000 0x10000>;
-		interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_0_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_SAI_0_MCLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
-		dma-names = "rx", "tx";
-		dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
-		power-domains = <&pd IMX_SC_R_SAI_0>,
-				<&pd IMX_SC_R_DMA_0_CH12>,
-				<&pd IMX_SC_R_DMA_0_CH13>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_sai1: sai@59050000 {
-		compatible = "fsl,imx8qm-sai";
-		reg = <0x59050000 0x10000>;
-		interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_1_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_SAI_1_MCLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
-		dma-names = "rx", "tx";
-		dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
-		power-domains = <&pd IMX_SC_R_SAI_1>,
-				<&pd IMX_SC_R_DMA_0_CH14>,
-				<&pd IMX_SC_R_DMA_0_CH15>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_sai2: sai@59060000 {
-		compatible = "fsl,imx8qm-sai";
-		reg = <0x59060000 0x10000>;
-		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_2_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_SAI_2_MCLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
-		dma-names = "rx";
-		dmas = <&edma0 16 0 1>;
-		power-domains = <&pd IMX_SC_R_SAI_2>,
-				<&pd IMX_SC_R_DMA_0_CH16>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_sai3: sai@59070000 {
-		compatible = "fsl,imx8qm-sai";
-		reg = <0x59070000 0x10000>;
-		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_3_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_SAI_3_MCLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
-		dma-names = "rx";
-		dmas = <&edma0 17 0 1>;
-		power-domains = <&pd IMX_SC_R_SAI_3>,
-				<&pd IMX_SC_R_DMA_0_CH17>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_asrc1: asrc@59800000 {
-		compatible = "fsl,imx8qm-asrc1";
-		reg = <0x59800000 0x10000>;
-		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
-			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
-			<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
-			<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "ipg", "mem",
-			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
-			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
-			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
-			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
-			"spba";
-		dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
-			<&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
-		dma-names = "rxa", "rxb", "rxc",
-				"txa", "txb", "txc";
-		fsl,asrc-rate  = <8000>;
-		fsl,asrc-width = <16>;
-		power-domains = <&pd IMX_SC_R_ASRC_1>,
-				<&pd IMX_SC_R_DMA_1_CH0>,
-				<&pd IMX_SC_R_DMA_1_CH1>,
-				<&pd IMX_SC_R_DMA_1_CH2>,
-				<&pd IMX_SC_R_DMA_1_CH3>,
-				<&pd IMX_SC_R_DMA_1_CH4>,
-				<&pd IMX_SC_R_DMA_1_CH5>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_sai4: sai@59820000 {
-		compatible = "fsl,imx8qm-sai";
-		reg = <0x59820000 0x10000>;
-		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_4_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_SAI_4_MCLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
-		dma-names = "rx", "tx";
-		dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
-		power-domains = <&pd IMX_SC_R_SAI_4>,
-				<&pd IMX_SC_R_DMA_1_CH8>,
-				<&pd IMX_SC_R_DMA_1_CH9>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_sai5: sai@59830000 {
-		compatible = "fsl,imx8qm-sai";
-		reg = <0x59830000 0x10000>;
-		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_5_IPG_CLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&adma_lpcg IMX_ADMA_LPCG_SAI_5_MCLK>,
-			<&clk IMX_CLK_DUMMY>,
-			<&clk IMX_CLK_DUMMY>;
-		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
-		dma-names = "tx";
-		dmas = <&edma1 10 0 0>;
-		power-domains = <&pd IMX_SC_R_SAI_5>,
-				<&pd IMX_SC_R_DMA_1_CH10>,
-				<&pd IMX_SC_R_AUDIO_CLK_0>,
-				<&pd IMX_SC_R_AUDIO_CLK_1>,
-				<&pd IMX_SC_R_AUDIO_PLL_0>,
-				<&pd IMX_SC_R_AUDIO_PLL_1>;
-		status = "disabled";
-	};
-
-	adma_amix: amix@59840000 {
-		compatible = "fsl,imx8qm-amix";
-		reg = <0x59840000 0x10000>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_AMIX_IPG_CLK>;
-		clock-names = "ipg";
-		power-domains = <&pd IMX_SC_R_AMIX>;
-		status = "disabled";
-	};
-
-	adma_mqs: mqs@59850000 {
-		compatible = "fsl,imx8qm-mqs";
-		reg = <0x59850000 0x10000>;
-		clocks = <&adma_lpcg IMX_ADMA_LPCG_MQS_IPG_CLK>,
-			<&adma_lpcg IMX_ADMA_LPCG_MQS_MCLK>;
-		clock-names = "core", "mclk";
-		power-domains = <&pd IMX_SC_R_MQS_0>;
-		status = "disabled";
-	};
-
-	i2c0_lpcg: clock-controller@5ac00000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5ac00000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "i2c0_lpcg_clk",
-				     "i2c0_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_I2C_0>;
-	};
-
-	i2c1_lpcg: clock-controller@5ac10000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5ac10000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "i2c1_lpcg_clk",
-				     "i2c1_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_I2C_1>;
-	};
-
-	i2c2_lpcg: clock-controller@5ac20000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5ac20000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "i2c2_lpcg_clk",
-				     "i2c2_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_I2C_2>;
-	};
-
-	i2c3_lpcg: clock-controller@5ac30000 {
-		compatible = "fsl,imx8qxp-lpcg";
-		reg = <0x5ac30000 0x10000>;
-		#clock-cells = <1>;
-		clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
-			 <&dma_ipg_clk>;
-		bit-offset = <0 16>;
-		clock-output-names = "i2c3_lpcg_clk",
-				     "i2c3_lpcg_ipg_clk";
-		power-domains = <&pd IMX_SC_R_I2C_3>;
-	};
-};
+#include "imx8-ss-audio.dtsi"
+#include "imx8-ss-dma.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
new file mode 100644
index 000000000000..64dcd6d05bdf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+audio_subsys: bus@59000000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x59000000 0x0 0x59000000 0x1000000>;
+
+	edma0: dma-controller@591F0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x59200000 0x10000>, /* asrc0 */
+			<0x59210000 0x10000>,
+			<0x59220000 0x10000>,
+			<0x59230000 0x10000>,
+			<0x59240000 0x10000>,
+			<0x59250000 0x10000>,
+			<0x59260000 0x10000>, /* esai0 rx */
+			<0x59270000 0x10000>, /* esai0 tx */
+			<0x59280000 0x10000>, /* spdif0 rx */
+			<0x59290000 0x10000>, /* spdif0 tx */
+			<0x592c0000 0x10000>, /* sai0 rx */
+			<0x592d0000 0x10000>, /* sai0 tx */
+			<0x592e0000 0x10000>, /* sai1 rx */
+			<0x592f0000 0x10000>, /* sai1 tx */
+			<0x59350000 0x10000>,
+			<0x59370000 0x10000>;
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <16>;
+		interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
+				<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
+				"edma0-chan2-rx", "edma0-chan3-tx",
+				"edma0-chan4-tx", "edma0-chan5-tx",
+				"edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
+				"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
+				"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
+				"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
+				"edma0-chan21-tx",		/* gpt5 */
+				"edma0-chan23-rx";		/* gpt7 */
+		status = "okay";
+	};
+
+	edma1: dma-controller@599F0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x59A00000 0x10000>, /* asrc1 */
+			<0x59A10000 0x10000>,
+			<0x59A20000 0x10000>,
+			<0x59A30000 0x10000>,
+			<0x59A40000 0x10000>,
+			<0x59A50000 0x10000>,
+			<0x59A80000 0x10000>, /* sai4 rx */
+			<0x59A90000 0x10000>, /* sai4 tx */
+			<0x59AA0000 0x10000>; /* sai5 tx */
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <9>;
+		interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
+				<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+		interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
+				"edma1-chan2-rx", "edma1-chan3-tx",
+				"edma1-chan4-tx", "edma1-chan5-tx",
+				"edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
+				"edma1-chan10-tx";                 /* sai5 */
+		status = "okay";
+	};
+
+	adma_acm: acm@59e00000 {
+		compatible = "nxp,imx8qxp-acm";
+		reg = <0x59e00000 0x1D0000>;
+		#clock-cells = <1>;
+		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_MCLK_OUT_0>,
+				<&pd IMX_SC_R_MCLK_OUT_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>,
+				<&pd IMX_SC_R_ASRC_0>,
+				<&pd IMX_SC_R_ASRC_1>,
+				<&pd IMX_SC_R_ESAI_0>,
+				<&pd IMX_SC_R_SAI_0>,
+				<&pd IMX_SC_R_SAI_1>,
+				<&pd IMX_SC_R_SAI_2>,
+				<&pd IMX_SC_R_SAI_3>,
+				<&pd IMX_SC_R_SAI_4>,
+				<&pd IMX_SC_R_SAI_5>,
+				<&pd IMX_SC_R_SPDIF_0>,
+				<&pd IMX_SC_R_MQS_0>;
+	};
+
+	adma_dsp: dsp@596e8000 {
+		compatible = "fsl,imx8qxp-dsp";
+		reg = <0x596e8000 0x88000>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+		clock-names = "ipg", "ocram", "core";
+		fsl,dsp-firmware = "imx/dsp/hifi4.bin";
+		power-domains = <&pd IMX_SC_R_MU_13A>,
+				<&pd IMX_SC_R_MU_13B>,
+				<&pd IMX_SC_R_DSP>,
+				<&pd IMX_SC_R_DSP_RAM>;
+		reserved-region = <&dsp_reserved>;
+		status = "disabled";
+	};
+
+	adma_asrc0: asrc@59000000 {
+		compatible = "fsl,imx8qm-asrc0";
+		reg = <0x59000000 0x10000>;
+		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
+			<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd IMX_SC_R_ASRC_0>,
+				<&pd IMX_SC_R_DMA_0_CH0>,
+				<&pd IMX_SC_R_DMA_0_CH1>,
+				<&pd IMX_SC_R_DMA_0_CH2>,
+				<&pd IMX_SC_R_DMA_0_CH3>,
+				<&pd IMX_SC_R_DMA_0_CH4>,
+				<&pd IMX_SC_R_DMA_0_CH5>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+        };
+
+	adma_esai0: esai@59010000 {
+		compatible = "fsl,imx8qm-esai";
+		reg = <0x59010000 0x10000>;
+		interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "core", "extal", "fsys", "spba";
+		dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd IMX_SC_R_ESAI_0>,
+				<&pd IMX_SC_R_DMA_0_CH6>,
+				<&pd IMX_SC_R_DMA_0_CH7>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_spdif0: spdif@59020000 {
+		compatible = "fsl,imx8qm-spdif";
+		reg = <0x59020000 0x10000>;
+		interrupts =  <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+			<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPDIF_0_GCLKW>, /* core */
+			<&clk IMX_CLK_DUMMY>, /* rxtx0 */
+			<&adma_lpcg IMX_ADMA_LPCG_SPDIF_0_TX_CLK>, /* rxtx1 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx2 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx3 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx4 */
+			<&clk IMX_ADMA_IPG_CLK_ROOT>, /* rxtx5 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx6 */
+			<&clk IMX_CLK_DUMMY>, /* rxtx7 */
+			<&clk IMX_CLK_DUMMY>; /* spba */
+		clock-names = "core", "rxtx0",
+				"rxtx1", "rxtx2",
+				"rxtx3", "rxtx4",
+				"rxtx5", "rxtx6",
+				"rxtx7", "spba";
+		dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd IMX_SC_R_SPDIF_0>,
+				<&pd IMX_SC_R_DMA_0_CH8>,
+				<&pd IMX_SC_R_DMA_0_CH9>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai0: sai@59040000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59040000 0x10000>;
+		interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_0_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_0>,
+				<&pd IMX_SC_R_DMA_0_CH12>,
+				<&pd IMX_SC_R_DMA_0_CH13>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai1: sai@59050000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59050000 0x10000>;
+		interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_1_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_1_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_1>,
+				<&pd IMX_SC_R_DMA_0_CH14>,
+				<&pd IMX_SC_R_DMA_0_CH15>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai2: sai@59060000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59060000 0x10000>;
+		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_2_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_2_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 16 0 1>;
+		power-domains = <&pd IMX_SC_R_SAI_2>,
+				<&pd IMX_SC_R_DMA_0_CH16>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai3: sai@59070000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59070000 0x10000>;
+		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_3_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_3_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 17 0 1>;
+		power-domains = <&pd IMX_SC_R_SAI_3>,
+				<&pd IMX_SC_R_DMA_0_CH17>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_asrc1: asrc@59800000 {
+		compatible = "fsl,imx8qm-asrc1";
+		reg = <0x59800000 0x10000>;
+		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+			<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
+			<&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd IMX_SC_R_ASRC_1>,
+				<&pd IMX_SC_R_DMA_1_CH0>,
+				<&pd IMX_SC_R_DMA_1_CH1>,
+				<&pd IMX_SC_R_DMA_1_CH2>,
+				<&pd IMX_SC_R_DMA_1_CH3>,
+				<&pd IMX_SC_R_DMA_1_CH4>,
+				<&pd IMX_SC_R_DMA_1_CH5>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai4: sai@59820000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59820000 0x10000>;
+		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_4_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_4_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_4>,
+				<&pd IMX_SC_R_DMA_1_CH8>,
+				<&pd IMX_SC_R_DMA_1_CH9>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_sai5: sai@59830000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x59830000 0x10000>;
+		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SAI_5_IPG_CLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&adma_lpcg IMX_ADMA_LPCG_SAI_5_MCLK>,
+			<&clk IMX_CLK_DUMMY>,
+			<&clk IMX_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "tx";
+		dmas = <&edma1 10 0 0>;
+		power-domains = <&pd IMX_SC_R_SAI_5>,
+				<&pd IMX_SC_R_DMA_1_CH10>,
+				<&pd IMX_SC_R_AUDIO_CLK_0>,
+				<&pd IMX_SC_R_AUDIO_CLK_1>,
+				<&pd IMX_SC_R_AUDIO_PLL_0>,
+				<&pd IMX_SC_R_AUDIO_PLL_1>;
+		status = "disabled";
+	};
+
+	adma_amix: amix@59840000 {
+		compatible = "fsl,imx8qm-amix";
+		reg = <0x59840000 0x10000>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_AMIX_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_AMIX>;
+		status = "disabled";
+	};
+
+	adma_mqs: mqs@59850000 {
+		compatible = "fsl,imx8qm-mqs";
+		reg = <0x59850000 0x10000>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_MQS_IPG_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_MQS_MCLK>;
+		clock-names = "core", "mclk";
+		power-domains = <&pd IMX_SC_R_MQS_0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
new file mode 100644
index 000000000000..2ab6cf556628
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+dma_subsys: bus@5a000000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
+
+	dma_ipg_clk: clock-dma-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <120000000>;
+		clock-output-names = "dma_ipg_clk";
+	};
+
+	lpspi0: spi@5a000000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x5a000000 0x10000>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPI0_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_SPI0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_ADMA_SPI0_CLK>;
+		assigned-clock-rates = <20000000>;
+		power-domains = <&pd IMX_SC_R_SPI_0>;
+		status = "disabled";
+	};
+
+	lpspi2: spi@5a020000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x5a020000 0x10000>;
+		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_SPI2_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_SPI2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_ADMA_SPI2_CLK>;
+		assigned-clock-rates = <20000000>;
+		power-domains = <&pd IMX_SC_R_SPI_2>;
+		status = "disabled";
+	};
+
+	lpuart0: serial@5a060000 {
+		reg = <0x5a060000 0x1000>;
+		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_ADMA_UART0_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd IMX_SC_R_UART_0>;
+		status = "disabled";
+	};
+
+	lpuart1: serial@5a070000 {
+		reg = <0x5a070000 0x1000>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_ADMA_UART1_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd IMX_SC_R_UART_1>,
+				<&pd IMX_SC_R_DMA_2_CH10>,
+				<&pd IMX_SC_R_DMA_2_CH11>;
+		power-domain-names = "uart", "rxdma", "txdma";
+		dma-names = "tx","rx";
+		dmas = <&edma2 11 0 0>,
+			<&edma2 10 0 1>;
+		status = "disabled";
+	};
+
+	lpuart2: serial@5a080000 {
+		reg = <0x5a080000 0x1000>;
+		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_ADMA_UART2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd IMX_SC_R_UART_2>,
+				<&pd IMX_SC_R_DMA_2_CH12>,
+				<&pd IMX_SC_R_DMA_2_CH13>;
+		power-domain-names = "uart", "rxdma", "txdma";
+		dma-names = "tx","rx";
+		dmas = <&edma2 13 0 0>,
+			<&edma2 12 0 1>;
+		status = "disabled";
+	};
+
+	lpuart3: serial@5a090000 {
+		reg = <0x5a090000 0x1000>;
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_ADMA_UART3_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd IMX_SC_R_UART_3>,
+				<&pd IMX_SC_R_DMA_2_CH14>,
+				<&pd IMX_SC_R_DMA_2_CH15>;
+		power-domain-names = "uart", "rxdma", "txdma";
+		dma-names = "tx","rx";
+		dmas = <&edma2 15 0 0>,
+			<&edma2 14 0 1>;
+		status = "disabled";
+	};
+
+	edma2: dma-controller@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
+		      <0x5a290000 0x10000>, /* channel9 UART0 tx */
+		      <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
+		      <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
+		      <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
+		      <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
+		      <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
+		      <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
+		#dma-cells = <3>;
+		dma-channels = <8>;
+		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+				  "edma2-chan10-rx", "edma2-chan11-tx",
+				  "edma2-chan12-rx", "edma2-chan13-tx",
+				  "edma2-chan14-rx", "edma2-chan15-tx";
+		status = "disabled";
+	};
+
+	uart0_lpcg: clock-controller@5a460000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a460000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "uart0_lpcg_baud_clk",
+				     "uart0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_UART_0>;
+	};
+
+	uart1_lpcg: clock-controller@5a470000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a470000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "uart1_lpcg_baud_clk",
+				     "uart1_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_UART_1>;
+	};
+
+	uart2_lpcg: clock-controller@5a480000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a480000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "uart2_lpcg_baud_clk",
+				     "uart2_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_UART_2>;
+	};
+
+	uart3_lpcg: clock-controller@5a490000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5a490000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "uart3_lpcg_baud_clk",
+				     "uart3_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_UART_3>;
+	};
+
+	i2c0: i2c@5a800000 {
+		reg = <0x5a800000 0x4000>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&i2c0_lpcg 0>;
+		clock-names = "per";
+		assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_I2C_0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@5a810000 {
+		reg = <0x5a810000 0x4000>;
+		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&i2c1_lpcg 0>;
+		clock-names = "per";
+		assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_I2C_1>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@5a820000 {
+		reg = <0x5a820000 0x4000>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&i2c2_lpcg 0>;
+		clock-names = "per";
+		assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_I2C_2>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@5a830000 {
+		reg = <0x5a830000 0x4000>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&i2c3_lpcg 0>;
+		clock-names = "per";
+		assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_I2C_3>;
+		status = "disabled";
+	};
+
+	flexcan1: can@5a8d0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x5a8d0000 0x10000>;
+		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd IMX_SC_R_CAN_0>;
+		/* SLSlice[4] */
+		fsl,clk-source= <0>;
+		status = "disabled";
+	};
+
+	flexcan2: can@5a8e0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x5a8e0000 0x10000>;
+		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		/* CAN1 shares CAN0's clock, to enable CAN0's clock it has
+		 * to be powered on, so CAN1 depends on CAN0's power domain.
+		 */
+		power-domains = <&pd IMX_SC_R_CAN_1>, <&pd IMX_SC_R_CAN_0>;
+		power-domain-names = "can_pd", "can_aux_pd";
+		/* SLSlice[4] */
+		fsl,clk-source = <0>;
+		status = "disabled";
+	};
+
+	flexcan3: can@5a8f0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x5a8f0000 0x10000>;
+		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_CLK>,
+			 <&adma_lpcg IMX_ADMA_LPCG_CAN0_IPG_PE_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_ADMA_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		/* CAN2 shares CAN0's clock, to enable CAN0's clock it has
+		 * to be powered on, so CAN2 depends on CAN0's power domain.
+		 */
+		power-domains = <&pd IMX_SC_R_CAN_2>, <&pd IMX_SC_R_CAN_0>;
+		power-domain-names = "can_pd", "can_aux_pd";
+		/* SLSlice[4] */
+		fsl,clk-source = <0>;
+		status = "disabled";
+	};
+
+	i2c0_lpcg: clock-controller@5ac00000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5ac00000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "i2c0_lpcg_clk",
+				     "i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_I2C_0>;
+	};
+
+	i2c1_lpcg: clock-controller@5ac10000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5ac10000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "i2c1_lpcg_clk",
+				     "i2c1_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_I2C_1>;
+	};
+
+	i2c2_lpcg: clock-controller@5ac20000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5ac20000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "i2c2_lpcg_clk",
+				     "i2c2_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_I2C_2>;
+	};
+
+	i2c3_lpcg: clock-controller@5ac30000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5ac30000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
+			 <&dma_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "i2c3_lpcg_clk",
+				     "i2c3_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_I2C_3>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index ee00202bd311..9c84117d3ba0 100755
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -12,7 +12,7 @@
 	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
 
 	chosen {
-		stdout-path = &adma_lpuart0;
+		stdout-path = &lpuart0;
 	};
 
 	memory@80000000 {
@@ -365,25 +365,25 @@
 	};
 };
 
-&adma_lpuart0 {
+&lpuart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
 	status = "okay";
 };
 
-&adma_lpuart1 {
+&lpuart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart1>;
 	status = "okay";
 };
 
-&adma_lpuart2 {
+&lpuart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart2>;
 	status = "okay";
 };
 
-&adma_lpuart3 {
+&lpuart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart3>;
 	status = "okay";
@@ -529,7 +529,7 @@
 	};
 };
 
-&adma_i2c1 {
+&i2c1 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	clock-frequency = <100000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
index c80303d5cc78..f0264f04f986 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi
@@ -4,34 +4,34 @@
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
 
-&adma_lpuart0 {
+&lpuart0 {
 	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 };
 
-&adma_lpuart1 {
+&lpuart1 {
 	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 };
 
-&adma_lpuart2 {
+&lpuart2 {
 	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 };
 
-&adma_lpuart3 {
+&lpuart3 {
 	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 };
 
-&adma_i2c0 {
+&i2c0 {
 	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 };
 
-&adma_i2c1 {
+&i2c1 {
 	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 };
 
-&adma_i2c2 {
+&i2c2 {
 	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 };
 
-&adma_i2c3 {
+&i2c3 {
 	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 156f9a8f2e70..d462591d2f04 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -33,10 +33,10 @@
 		mmc1 = &usdhc2;
 		mmc2 = &usdhc3;
 		mu1 = &lsio_mu1;
-		serial0 = &adma_lpuart0;
-		serial1 = &adma_lpuart1;
-		serial2 = &adma_lpuart2;
-		serial3 = &adma_lpuart3;
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
 		isi0 = &isi_0;
 		isi1 = &isi_1;
 		isi2 = &isi_2;