LF-202-5 arm64: dts: imx8qm: add basic dom0/domu dts

Add basic dom0/domu dts for xen on i.MX8QM MEK.
Dual display works and emmc passthrough to DomU.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>

4 files changed, 804 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index b568a4a0e860..691831b827c2 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \
 			  imx8qm-lpddr4-val-ca72.dtb imx8qm-ddr4-val.dtb \
 			  imx8qm-lpddr4-val-lpspi.dtb imx8qm-lpddr4-val-lpspi-slave.dtb \
 			  imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb \
 			  imx8dxl-phantom-mek-rpmsg.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts
new file mode 100644
index 000000000000..233f8f942188
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-dom0.dts
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8qm-mek.dts"
+#include "imx8qm-xen.dtsi"
+
+/ {
+	model = "Freescale i.MX8QM MEK";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		stdout-path = &lpuart0;
+
+		/* Could be updated by U-Boot */
+		module@0 {
+			bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw  rootwait";
+			compatible = "xen,linux-zimage", "xen,multiboot-module";
+			reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>;
+               };
+	};
+
+	domu {
+		/*
+		 * There are 5 MUs, 0A is used by Dom0, 1A is used
+		 * by ATF, so for DomU, 2A/3A/4A could be used.
+		 * SC_R_MU_0A
+		 * SC_R_MU_1A
+		 * SC_R_MU_2A
+		 * SC_R_MU_3A
+		 * SC_R_MU_4A
+		 * The rsrcs and pads will be configured by uboot scu_rm cmd
+		 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		doma {
+			compatible = "xen,domu";
+			/*
+			 * The name entry in VM configuration file
+			 * needs to be same as here.
+			 */
+			domain_name = "DomU";
+			/*
+			 * The reg property will be updated by U-Boot to
+			 * reflect the partition id.
+			 */
+			reg = <0>;
+			init_on_rsrcs = <
+				IMX_SC_R_MU_2A
+			>;
+			rsrcs = <
+				IMX_SC_R_MU_2A
+				IMX_SC_R_GPU_0_PID0
+				IMX_SC_R_GPU_0_PID1
+				IMX_SC_R_GPU_0_PID2
+				IMX_SC_R_GPU_0_PID3
+				IMX_SC_R_LVDS_0
+				IMX_SC_R_LVDS_0_I2C_0
+				IMX_SC_R_LVDS_0_PWM_0
+				IMX_SC_R_DC_0
+				IMX_SC_R_DC_0_BLIT0
+				IMX_SC_R_DC_0_BLIT1
+				IMX_SC_R_DC_0_BLIT2
+				IMX_SC_R_DC_0_BLIT_OUT
+				IMX_SC_R_DC_0_WARP
+				IMX_SC_R_DC_0_VIDEO0
+				IMX_SC_R_DC_0_VIDEO1
+				IMX_SC_R_DC_0_FRAC0
+				IMX_SC_R_DC_0_PLL_0
+				IMX_SC_R_DC_0_PLL_1
+				IMX_SC_R_SDHC_0
+			>;
+			pads = <
+				/* i2c1_lvds1 */
+				IMX8QM_LVDS0_I2C1_SCL
+				IMX8QM_LVDS0_I2C1_SDA
+				/* emmc */
+				IMX8QM_EMMC0_CLK
+				IMX8QM_EMMC0_CMD
+				IMX8QM_EMMC0_DATA0
+				IMX8QM_EMMC0_DATA1
+				IMX8QM_EMMC0_DATA2
+				IMX8QM_EMMC0_DATA3
+				IMX8QM_EMMC0_DATA4
+				IMX8QM_EMMC0_DATA5
+				IMX8QM_EMMC0_DATA6
+				IMX8QM_EMMC0_DATA7
+				IMX8QM_EMMC0_STROBE
+				IMX8QM_EMMC0_RESET_B
+
+				/* lvds pwm */
+				IMX8QM_LVDS0_GPIO00
+			>;
+		};
+	};
+
+
+	/* Interrupt 33 is not used, use it virtual PL031 */
+	rtc0: rtc@23000000 {
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		xen,passthrough;
+	};
+};
+
+&{/reserved-memory} {
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0xa8000000 0 0x58000000>;
+			linux,cma-default;
+		};
+};
+
+&smmu {
+	mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, <&usdhc1 0x12>;
+};
+
+&gpu_3d0{
+	#stream-id-cells = <1>;
+	iommus = <&smmu>;
+	xen,passthrough;
+};
+
+&gpu_3d1{
+	status = "okay";
+};
+
+&imx8_gpu_ss {
+	cores = <&gpu_3d1>;
+	reg = <0xa8000000 0x58000000>, <0x0 0x10000000>;
+	status = "okay";
+};
+
+&lsio_mu1 {
+	/* not map for dom0, dom0 will mmio trap to xen */
+	xen,no-map;
+};
+
+/ {
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&dpu2_disp0>, <&dpu2_disp1>;
+	};
+};
+
+&dc0_irqsteer {
+	reg = <0x56000000 0x20000>;
+	xen,passthrough;
+};
+
+&dc0_pc {
+	xen,passthrough;
+};
+
+&dc0_prg1 {
+	xen,passthrough;
+};
+
+&dc0_prg2 {
+	xen,passthrough;
+};
+
+&dc0_prg3 {
+	xen,passthrough;
+};
+
+&dc0_prg4 {
+	xen,passthrough;
+};
+
+&dc0_prg5 {
+	xen,passthrough;
+};
+
+&dc0_prg6 {
+	xen,passthrough;
+};
+
+&dc0_prg7 {
+	xen,passthrough;
+};
+
+&dc0_prg8 {
+	xen,passthrough;
+};
+
+&dc0_prg9 {
+	xen,passthrough;
+};
+
+&dc0_dpr1_channel1 {
+	xen,passthrough;
+};
+
+&dc0_dpr1_channel2 {
+	xen,passthrough;
+};
+
+&dc0_dpr1_channel3 {
+	xen,passthrough;
+};
+
+&dc0_dpr2_channel1 {
+	xen,passthrough;
+};
+
+&dc0_dpr2_channel2 {
+	xen,passthrough;
+};
+
+&dc0_dpr2_channel3 {
+	xen,passthrough;
+};
+
+&dpu1 {
+	xen,passthrough;
+	#stream-id-cells = <1>;
+	iommus = <&smmu>;
+};
+
+&irqsteer_lvds0 {
+	xen,passthrough;
+};
+
+&lvds0_region {
+	xen,passthrough;
+};
+
+&i2c1_lvds0 {
+	xen,passthrough;
+};
+
+&ldb1_phy {
+	xen,passthrough;
+};
+
+&ldb1 {
+	xen,passthrough;
+};
+
+&usdhc1 {
+	xen,passthrough;
+	#stream-id-cells = <1>;
+	iommus = <&smmu>;
+};
+
+&lsio_mu2 {
+	xen,passthrough;
+};
+
+&lsio_gpio1 {
+	xen,shared;
+};
+
+&lsio_gpio4 {
+	xen,shared;
+};
+
+&gpio0_mipi_csi0 {
+	xen,shared;
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts
new file mode 100644
index 000000000000..dd4eda2fae48
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-domu.dts
@@ -0,0 +1,470 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/usb/pd.h>
+
+/*
+ * At current stage, M41 is not ready to communicate with XEN, so we
+ * we need a way to tell XEN uboot is running or linux is running.
+ * XEN will check the contents of this area.
+ * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux
+ * touch this area.
+ */
+/memreserve/ 0x80000000 0x1000;
+
+/ {
+	model = "Freescale i.MX8QM DOMU";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm";
+	interrupt-parent = <&gic>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	aliases {
+		mmc0 = &usdhc1;
+		dpu0 = &dpu1;
+		ldb0 = &ldb1;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			enable-method = "psci";
+			reg = <0x0 0x0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			enable-method = "psci";
+			reg = <0x0 0x1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			enable-method = "psci";
+			reg = <0x0 0x2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			enable-method = "psci";
+			reg = <0x0 0x3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "hvc";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* Will be updated by U-Boot or XEN TOOL */
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+	};
+
+	/*
+	 * The reserved memory will be used when using U-Boot loading android
+	 * image. For booting kernel using xl tool, pass args:
+	 * cma=960M@2400M-3584M
+	 * For the rpmsg_reserved area, need xl tool to create for non-android.
+	 */
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		passthrough;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0x96000000 0 0x3c000000>;
+			linux,cma-default;
+		};
+	};
+
+	gic: interrupt-controller@3001000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <0x0>;
+		interrupt-controller;
+		redistributor-stride = <0x20000>;
+		#redistributor-regions = <0x1>;
+		reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x3020000 0 0x1000000>; /* GICR */
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+		linux,phandle = <0xfde8>;
+		phandle = <0xfde8>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupt-parent = <&gic>;
+		clock-frequency = <8000000>;
+	};
+
+	hypervisor {
+		compatible = "xen,xen-4.11", "xen,xen";
+		reg = <0x0 0x38000000 0x0 0x1000000>;
+		interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupt-parent = <&gic>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk0: clock@0 {
+		        compatible = "fixed-clock";
+		        reg = <0>;
+		        #clock-cells = <0>;
+		        clock-frequency = <24000000>;
+		};
+	};
+
+	rtc0: rtc@23000000 {
+		compatible = "arm,pl031", "arm,primecell";
+		reg = <0x0 0x23000000 0x0 0x1000>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk0>;
+		clock-names = "apb_pclk";
+	};
+
+	passthrough {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		clk_dummy: clock-dummy {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "clk_dummy";
+		};
+
+		xtal32k: clock-xtal32k {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "xtal_32KHz";
+		};
+
+		xtal24m: clock-xtal24m {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "xtal_24MHz";
+		};
+
+		scu {
+			compatible = "fsl,imx-scu";
+			mbox-names = "tx0", "tx1", "tx2", "tx3",
+				     "rx0", "rx1", "rx2", "rx3",
+				     "gip3";
+			mboxes = <&lsio_mu2 0 0
+				  &lsio_mu2 0 1
+				  &lsio_mu2 0 2
+				  &lsio_mu2 0 3
+				  &lsio_mu2 1 0
+				  &lsio_mu2 1 1
+				  &lsio_mu2 1 2
+				  &lsio_mu2 1 3
+				  &lsio_mu2 3 3>;
+
+			pd: imx8qx-pd {
+				compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
+				#power-domain-cells = <1>;
+			};
+
+			clk: clock-controller {
+				compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
+				#clock-cells = <2>;
+				clocks = <&xtal32k &xtal24m>;
+				clock-names = "xtal_32KHz", "xtal_24Mhz";
+			};
+
+			iomuxc: pinctrl {
+				compatible = "fsl,imx8qm-iomuxc";
+			};
+
+		};
+
+		#include "imx8-ss-conn.dtsi"
+		#include "imx8-ss-lsio.dtsi"
+		#include "imx8-ss-dc0.dtsi"
+		#include "imx8-ss-dc1.dtsi"
+		#include "imx8-ss-gpu0.dtsi"
+		#include "imx8-ss-gpu1.dtsi"
+
+		display-subsystem {
+			compatible = "fsl,imx-display-subsystem";
+			ports = <&dpu1_disp0>, <&dpu1_disp1>;
+		};
+
+		lvds_backlight0: lvds_backlight@0 {
+			compatible = "pwm-backlight";
+			pwms = <&pwm_lvds0 0 100000 0>;
+
+			brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+					     10 11 12 13 14 15 16 17 18 19
+					     20 21 22 23 24 25 26 27 28 29
+					     30 31 32 33 34 35 36 37 38 39
+					     40 41 42 43 44 45 46 47 48 49
+					     50 51 52 53 54 55 56 57 58 59
+					     60 61 62 63 64 65 66 67 68 69
+					     70 71 72 73 74 75 76 77 78 79
+					     80 81 82 83 84 85 86 87 88 89
+					     90 91 92 93 94 95 96 97 98 99
+					    100>;
+			default-brightness-level = <80>;
+		};
+	};
+};
+
+#include "imx8qm-ss-conn.dtsi"
+#include "imx8qm-ss-lsio.dtsi"
+#include "imx8qm-ss-dc.dtsi"
+#include "imx8qm-ss-gpu.dtsi"
+#include "imx8qm-ss-lvds.dtsi"
+#include "imx8qm-ss-hdmi.dtsi"
+
+&lvds1_subsys {
+	xen,passthrough;
+};
+
+&hdmi_subsys {
+	xen,passthrough;
+};
+
+&lsio_mu1 {
+	status = "disabled";
+};
+
+&lsio_mu2 {
+	status = "okay";
+};
+
+&pwm_lvds0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm_lvds0>;
+	status = "okay";
+};
+
+&i2c1_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+
+		port {
+			it6263_0_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&ldb1_phy {
+	status="okay";
+};
+
+&ldb1 {
+	status="okay";
+
+	lvds-channel@0 {
+		fsl,data-mapping = "jeida";
+		fsl,data-width = <24>;
+		status = "okay";
+
+		port@1 {
+			reg = <1>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&it6263_0_in>;
+			};
+		};
+	};
+};
+
+&dc0_pc {
+	status="okay";
+};
+
+&dc0_prg1 {
+	status="okay";
+};
+
+&dc0_prg2 {
+	status="okay";
+};
+
+&dc0_prg3 {
+	status="okay";
+};
+
+&dc0_prg4 {
+	status="okay";
+};
+
+&dc0_prg5 {
+	status="okay";
+};
+
+&dc0_prg6 {
+	status="okay";
+};
+
+&dc0_prg7 {
+	status="okay";
+};
+
+&dc0_prg8 {
+	status="okay";
+};
+
+&dc0_prg9 {
+	status="okay";
+};
+
+&dc0_dpr1_channel1 {
+	status="okay";
+};
+
+&dc0_dpr1_channel2 {
+	status="okay";
+};
+
+&dc0_dpr1_channel3 {
+	status="okay";
+};
+
+&dc0_dpr2_channel1 {
+	status="okay";
+};
+
+&dc0_dpr2_channel2 {
+	status="okay";
+};
+
+&dc0_dpr2_channel3 {
+	status="okay";
+};
+
+&dpu1 {
+	status="okay";
+};
+
+&gpu_3d0 {
+	status = "okay";
+};
+
+&gpu_3d1 {
+	status = "disabled";
+};
+
+&imx8_gpu_ss {
+	/* xen guests have 2GB of low RAM @ 2GB */
+	reg = <0x80000000 0x80000000>, <0x0 0x10000000>;
+	reg-names = "phys_baseaddr", "contiguous_mem";
+	cores = <&gpu_3d0>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_pwm_lvds0: pwmlvds0grp {
+		fsl,pins = <
+			IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT		0x00000020
+		>;
+	};
+
+	pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+		fsl,pins = <
+			IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
+			IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
+			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
+			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
+			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
+			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
+			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
+			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
+			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
+			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
+			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
+			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
+		>;
+	};
+};
+
+&usdhc1 {
+	/delete-property/ iommus;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	no-sd;
+	no-sdio;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	/delete-property/ iommus;
+	status = "disabled";
+};
+
+&usdhc3 {
+	/delete-property/ iommus;
+	status = "disabled";
+};
+
+&fec1 {
+	/delete-property/ iommus;
+	status = "disabled";
+};
+
+&fec2 {
+	/delete-property/ iommus;
+	status = "disabled";
+};
+
+&usbotg3 {
+	/delete-property/ iommus;
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi
new file mode 100644
index 000000000000..96656584b53b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-xen.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&usdhc1 {
+	/delete-property/ iommus;
+};
+
+&usdhc2 {
+	/delete-property/ iommus;
+};
+
+&usdhc3 {
+	/delete-property/ iommus;
+};
+
+&fec1 {
+	/delete-property/ iommus;
+};
+
+&fec2 {
+	/delete-property/ iommus;
+};
+
+&sata {
+	/delete-property/ iommus;
+};
+
+&sata {
+	/delete-property/ iommus;
+};
+
+&usbotg3 {
+	/delete-property/ iommus;
+};
+
+&smmu {
+	/* xen only supports legacy bindings for now */
+	#iommu-cells = <0>;
+};
+
+&dpu1 {
+	fsl,sc_rsrc_id = <IMX_SC_R_DC_0_BLIT0>,
+			 <IMX_SC_R_DC_0_BLIT1>,
+			 <IMX_SC_R_DC_0_BLIT2>,
+			 <IMX_SC_R_DC_0_BLIT_OUT>,
+			 <IMX_SC_R_DC_0_WARP>,
+			 <IMX_SC_R_DC_0_VIDEO0>,
+			 <IMX_SC_R_DC_0_VIDEO1>,
+			 <IMX_SC_R_DC_0_FRAC0>,
+			 <IMX_SC_R_DC_0>;
+};
+
+&dpu2 {
+	fsl,sc_rsrc_id = <IMX_SC_R_DC_1_BLIT0>,
+			 <IMX_SC_R_DC_1_BLIT1>,
+			 <IMX_SC_R_DC_1_BLIT2>,
+			 <IMX_SC_R_DC_1_BLIT_OUT>,
+			 <IMX_SC_R_DC_1_WARP>,
+			 <IMX_SC_R_DC_1_VIDEO0>,
+			 <IMX_SC_R_DC_1_VIDEO1>,
+			 <IMX_SC_R_DC_1_FRAC0>,
+			 <IMX_SC_R_DC_1>;
+};