diff options
| author | Xinyu Chen <xinyu.chen@freescale.com> | 2012-11-08 10:24:56 +0800 |
|---|---|---|
| committer | Xinyu Chen <xinyu.chen@freescale.com> | 2012-11-08 10:24:56 +0800 |
| commit | ac758db7a1ff13fbde98f4f3d1d2ac2c77780ccf (patch) | |
| tree | 47df51297eaaf05ed6abe31df318e799b3946eb7 /arch | |
| parent | 249d44a6a33b134efd248e5a6ab759c4218de0de (diff) | |
| parent | fa610478f592b1a65fe170848b9d2226cd32a254 (diff) | |
Merge remote branch 'fsl-linux-sdk/imx_3.0.35' into imx_3.0.35_android
Conflicts:
arch/arm/plat-mxc/dvfs_core.c
drivers/input/keyboard/mpr121.c
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
include/linux/i2c/mpr.h
sound/soc/imx/imx-wm8962.c
Diffstat (limited to 'arch')
34 files changed, 984 insertions, 327 deletions
diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig index 173fcc874cd1..55cc89c7d735 100644 --- a/arch/arm/configs/imx6_defconfig +++ b/arch/arm/configs/imx6_defconfig @@ -317,6 +317,7 @@ CONFIG_MACH_MX6Q_SABREAUTO=y # CONFIG_IMX_PCIE is not set CONFIG_USB_EHCI_ARC_H1=y # CONFIG_MX6_INTER_LDO_BYPASS is not set +# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set CONFIG_ISP1504_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set CONFIG_MXC_PWM=y @@ -383,6 +384,7 @@ CONFIG_ARM_GIC=y # # Bus support # +CONFIG_ARM_AMBA=y # CONFIG_PCI_SYSCALL is not set # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set @@ -722,8 +724,10 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -734,6 +738,10 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set @@ -742,6 +750,9 @@ CONFIG_MTD_CFI_I2=y # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -773,7 +784,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_GPMI_NAND is not set +CONFIG_MTD_NAND_GPMI_NAND=y # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set @@ -1057,7 +1068,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_MXC is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -1115,6 +1125,7 @@ CONFIG_INPUT_ISL29023=y # CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_SERIO_ALTERA_PS2 is not set @@ -1146,6 +1157,8 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX3107 is not set CONFIG_SERIAL_IMX=y @@ -1219,6 +1232,7 @@ CONFIG_SPI_BITBANG=y CONFIG_SPI_IMX_VER_2_3=y CONFIG_SPI_IMX=y # CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX_PCI is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_DESIGNWARE is not set @@ -1254,6 +1268,7 @@ CONFIG_GPIO_SYSFS=y # # CONFIG_GPIO_BASIC_MMIO is not set # CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_PL061 is not set # # I2C GPIO expanders: @@ -1405,6 +1420,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set # CONFIG_MPCORE_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set CONFIG_IMX2_WDT=y @@ -1623,6 +1639,7 @@ CONFIG_MXC_CAMERA_OV8820_MIPI=m CONFIG_MXC_CAMERA_OV5642=m CONFIG_MXC_TVIN_ADV7180=m CONFIG_MXC_CAMERA_OV5640_MIPI=m +# CONFIG_MXC_MIPI_CSI2_TVIN_ADV7280 is not set CONFIG_MXC_CAMERA_SENSOR_CLK=m CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m CONFIG_MXC_IPU_PRP_ENC=m @@ -1726,6 +1743,7 @@ CONFIG_FB_MODE_HELPERS=y # # Frame buffer hardware drivers # +# CONFIG_FB_ARMCLCD is not set # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_TMIO is not set @@ -1815,6 +1833,7 @@ CONFIG_SND_DRIVERS=y # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=y @@ -1828,7 +1847,7 @@ CONFIG_SND_IMX_SOC=y CONFIG_SND_MXC_SOC_MX2=y CONFIG_SND_MXC_SOC_SPDIF_DAI=y CONFIG_SND_SOC_IMX_SGTL5000=y -CONFIG_SND_SOC_IMX_WM8958=y +# CONFIG_SND_SOC_IMX_WM8958 is not set CONFIG_SND_SOC_IMX_WM8962=y CONFIG_SND_SOC_IMX_CS42888=y # CONFIG_SND_SOC_IMX_SI4763 is not set @@ -1836,13 +1855,11 @@ CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_IMX_HDMI=y CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM_HUBS=y CONFIG_SND_SOC_MXC_HDMI=y CONFIG_SND_SOC_MXC_SPDIF=y CONFIG_SND_SOC_SGTL5000=y CONFIG_SND_SOC_CS42888=y CONFIG_SND_SOC_WM8962=y -CONFIG_SND_SOC_WM8994=y # CONFIG_SOUND_PRIME is not set CONFIG_AC97_BUS=y CONFIG_HID_SUPPORT=y @@ -2082,6 +2099,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # # MMC/SD/SDIO Host Controller Drivers # +# CONFIG_MMC_ARMMMCI is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PLTFM=y @@ -2203,18 +2221,21 @@ CONFIG_RTC_DRV_SNVS=y # # on-CPU RTC drivers # +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set # # DMA Devices # +# CONFIG_AMBA_PL08X is not set # CONFIG_DW_DMAC is not set CONFIG_MXC_PXP_V2=y CONFIG_MXC_PXP_CLIENT_DEVICE=y # CONFIG_TIMB_DMA is not set CONFIG_IMX_SDMA=y -# CONFIG_MXS_DMA is not set +CONFIG_MXS_DMA=y CONFIG_DMA_ENGINE=y # @@ -2550,7 +2571,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_STRICT_DEVMEM is not set CONFIG_ARM_UNWIND=y # CONFIG_DEBUG_USER is not set -# CONFIG_OC_ETM is not set +CONFIG_OC_ETM=y # # Security options @@ -2674,6 +2695,9 @@ CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y # CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y # CONFIG_BINARY_PRINTF is not set # diff --git a/arch/arm/configs/imx6_updater_defconfig b/arch/arm/configs/imx6_updater_defconfig index 02b3707f62d0..06ffbc56eee5 100644 --- a/arch/arm/configs/imx6_updater_defconfig +++ b/arch/arm/configs/imx6_updater_defconfig @@ -316,6 +316,7 @@ CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_MACH_MX6Q_ARM2=y CONFIG_MACH_MX6SL_ARM2=y +# CONFIG_MACH_MX6SL_EVK is not set CONFIG_MACH_MX6Q_SABRELITE=y CONFIG_MACH_MX6Q_SABRESD=y CONFIG_MACH_MX6Q_SABREAUTO=y @@ -325,6 +326,7 @@ CONFIG_MACH_MX6Q_SABREAUTO=y # # CONFIG_IMX_PCIE is not set # CONFIG_MX6_INTER_LDO_BYPASS is not set +# CONFIG_MX6_CLK_FOR_BOOTUI_TRANS is not set CONFIG_ISP1504_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set CONFIG_MXC_PWM=y @@ -392,6 +394,7 @@ CONFIG_ARM_GIC=y # # Bus support # +CONFIG_ARM_AMBA=y # CONFIG_PCI_SYSCALL is not set # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set @@ -697,8 +700,10 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -709,6 +714,10 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set @@ -717,6 +726,9 @@ CONFIG_MTD_CFI_I2=y # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -748,7 +760,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_GPMI_NAND is not set +CONFIG_MTD_NAND_GPMI_NAND=y # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set @@ -1053,6 +1065,8 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX3107 is not set CONFIG_SERIAL_IMX=y @@ -1126,6 +1140,7 @@ CONFIG_SPI_BITBANG=y CONFIG_SPI_IMX_VER_2_3=y CONFIG_SPI_IMX=y # CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX_PCI is not set # CONFIG_SPI_XILINX is not set # CONFIG_SPI_DESIGNWARE is not set @@ -1161,6 +1176,7 @@ CONFIG_GPIOLIB=y # # CONFIG_GPIO_BASIC_MMIO is not set # CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_PL061 is not set # # I2C GPIO expanders: @@ -1205,6 +1221,7 @@ CONFIG_POWER_SUPPLY=y # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set +# CONFIG_SABRESD_MAX8903 is not set # CONFIG_CHARGER_GPIO is not set # CONFIG_HWMON is not set CONFIG_THERMAL=y @@ -1215,6 +1232,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set # CONFIG_MAX63XX_WATCHDOG is not set CONFIG_IMX2_WDT=y @@ -1417,17 +1435,10 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_VIVI is not set # CONFIG_VIDEO_MXC_CAMERA is not set -# CONFIG_MXC_CAMERA_MICRON111 is not set -# CONFIG_MXC_CAMERA_OV2640 is not set -# CONFIG_MXC_CAMERA_OV3640 is not set -# CONFIG_MXC_CAMERA_OV5640 is not set -# CONFIG_MXC_CAMERA_OV8820_MIPI is not set -# CONFIG_MXC_CAMERA_OV5642 is not set -# CONFIG_MXC_TVIN_ADV7180 is not set -# CONFIG_MXC_IPU_DEVICE_QUEUE_SDC is not set CONFIG_VIDEO_MXC_OUTPUT=y CONFIG_VIDEO_MXC_IPU_OUTPUT=y # CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set # CONFIG_VIDEO_MXC_OPL is not set # CONFIG_VIDEO_CPIA2 is not set # CONFIG_VIDEO_TIMBERDALE is not set @@ -1467,6 +1478,7 @@ CONFIG_FB_MODE_HELPERS=y # # Frame buffer hardware drivers # +# CONFIG_FB_ARMCLCD is not set # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_TMIO is not set @@ -1489,6 +1501,7 @@ CONFIG_FB_MXC_LDB=y # CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set # CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set # CONFIG_FB_MXC_SII902X is not set +# CONFIG_FB_MXC_SII902X_ELCDIF is not set # CONFIG_FB_MXC_CH7026 is not set # CONFIG_FB_MXC_TVOUT_CH7024 is not set # CONFIG_FB_MXC_ASYNC_PANEL is not set @@ -1546,6 +1559,7 @@ CONFIG_SND_DRIVERS=y # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set CONFIG_SND_SPI=y CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set @@ -1794,6 +1808,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # # MMC/SD/SDIO Host Controller Drivers # +# CONFIG_MMC_ARMMMCI is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PLTFM=y @@ -1879,17 +1894,20 @@ CONFIG_RTC_DRV_SNVS=y # # on-CPU RTC drivers # +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set # # DMA Devices # +# CONFIG_AMBA_PL08X is not set # CONFIG_DW_DMAC is not set # CONFIG_MXC_PXP_V2 is not set # CONFIG_TIMB_DMA is not set CONFIG_IMX_SDMA=y -# CONFIG_MXS_DMA is not set +CONFIG_MXS_DMA=y CONFIG_DMA_ENGINE=y # @@ -1981,6 +1999,7 @@ CONFIG_MXC_IPU_V3H=y # CONFIG_MXC_VPU=y # CONFIG_MXC_VPU_DEBUG is not set +# CONFIG_MX6_VPU_352M is not set # # MXC Asynchronous Sample Rate Converter support @@ -2253,7 +2272,7 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_STRICT_DEVMEM is not set CONFIG_ARM_UNWIND=y # CONFIG_DEBUG_USER is not set -# CONFIG_OC_ETM is not set +CONFIG_OC_ETM=y # # Security options diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig index ac7afdfdf5ff..41f43e5c0d63 100644 --- a/arch/arm/configs/imx6s_defconfig +++ b/arch/arm/configs/imx6s_defconfig @@ -1620,7 +1620,7 @@ CONFIG_MXC_CAMERA_OV5640=y # CONFIG_MXC_CAMERA_OV5640_MIPI is not set CONFIG_MXC_CAMERA_SENSOR_CLK=y CONFIG_VIDEO_MXC_OUTPUT=y -# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +CONFIG_VIDEO_MXC_PXP_V4L2=y # CONFIG_VIDEO_MXC_OPL is not set # CONFIG_VIDEO_CPIA2 is not set # CONFIG_VIDEO_TIMBERDALE is not set diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 519f13cd7116..0d3de152c725 100755 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -24,7 +24,7 @@ #include <linux/delay.h> #include <linux/gpio.h> #include <linux/i2c.h> -#include <linux/i2c/mpr.h> +#include <linux/i2c/mpr121_touchkey.h> #include <linux/fsl_devices.h> #include <linux/ahci_platform.h> #include <linux/regulator/consumer.h> @@ -653,14 +653,14 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { }; -static u16 smd_touchkey_martix[4] = { +static unsigned short smd_touchkey_martix[4] = { KEY_BACK, KEY_HOME, KEY_MENU, KEY_SEARCH, }; static struct mpr121_platform_data mpr121_keyboard_platdata = { - .keycount = ARRAY_SIZE(smd_touchkey_martix), + .keymap_size = ARRAY_SIZE(smd_touchkey_martix), .vdd_uv = 3300000, - .matrix = smd_touchkey_martix, + .keymap = smd_touchkey_martix, }; static int mag3110_position = 6; diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c index 883ec3e5bbdb..12f87b526253 100644 --- a/arch/arm/mach-mx6/board-mx6q_arm2.c +++ b/arch/arm/mach-mx6/board-mx6q_arm2.c @@ -164,6 +164,7 @@ static struct clk *sata_clk; static int esai_record; static int sgtl5000_en; static int spdif_en; +static int gpmi_en; static int flexcan_en; static int disable_mipi_dsi; @@ -1954,6 +1955,14 @@ static int __init early_enable_spdif(char *p) early_param("spdif", early_enable_spdif); +static int __init early_enable_gpmi(char *p) +{ + gpmi_en = 1; + return 0; +} + +early_param("gpmi", early_enable_gpmi); + static int __init early_enable_can(char *p) { flexcan_en = 1; @@ -2206,7 +2215,8 @@ static void __init mx6_arm2_init(void) imx6q_add_viim(); imx6q_add_imx2_wdt(0, NULL); imx6q_add_dma(); - imx6q_add_gpmi(&mx6_gpmi_nand_platform_data); + if (gpmi_en) + imx6q_add_gpmi(&mx6_gpmi_nand_platform_data); imx6q_add_dvfs_core(&arm2_dvfscore_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c index 7fe269bc0f6f..6caaa708d4a9 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c @@ -30,11 +30,8 @@ #include <linux/fsl_devices.h> #include <linux/smsc911x.h> #include <linux/spi/spi.h> -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) #include <linux/spi/flash.h> -#else #include <linux/mtd/physmap.h> -#endif #include <linux/i2c.h> #include <linux/i2c/pca953x.h> #include <linux/ata.h> @@ -99,6 +96,7 @@ #define SABREAUTO_ANDROID_MENU IMX_GPIO_NR(2, 12) #define SABREAUTO_ANDROID_VOLUP IMX_GPIO_NR(2, 15) #define SABREAUTO_CAP_TCH_INT IMX_GPIO_NR(2, 28) +#define SABREAUTO_eCOMPASS_INT IMX_GPIO_NR(2, 29) #define SABREAUTO_ECSPI1_CS1 IMX_GPIO_NR(3, 19) #define SABREAUTO_DISP0_PWR IMX_GPIO_NR(3, 24) #define SABREAUTO_DISP0_I2C_EN IMX_GPIO_NR(3, 28) @@ -140,6 +138,7 @@ extern char *soc_reg_id; extern char *pu_reg_id; static int mma8451_position = 3; +static int mag3110_position = 2; static struct clk *sata_clk; static int mipi_sensor; static int can0_enable; @@ -330,10 +329,16 @@ mx6q_sabreauto_anatop_thermal_data __initconst = { .name = "anatop_thermal", }; +static const struct imxuart_platform_data mx6_bt_uart_data __initconst = { + .flags = IMXUART_HAVE_RTSCTS | IMXUART_SDMA, + .dma_req_rx = MX6Q_DMA_REQ_UART3_RX, + .dma_req_tx = MX6Q_DMA_REQ_UART3_TX, +}; + static inline void mx6q_sabreauto_init_uart(void) { imx6q_add_imx_uart(1, NULL); - imx6q_add_imx_uart(2, NULL); + imx6q_add_imx_uart(2, &mx6_bt_uart_data); imx6q_add_imx_uart(3, NULL); } @@ -400,7 +405,6 @@ static const struct spi_imx_master mx6q_sabreauto_spi_data __initconst = { .num_chipselect = ARRAY_SIZE(mx6q_sabreauto_spi_cs), }; -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) static struct mtd_partition m25p32_partitions[] = { { .name = "bootloader", @@ -421,7 +425,6 @@ static struct flash_platform_data m25p32_spi_flash_data = { }; static struct spi_board_info m25p32_spi0_board_info[] __initdata = { -#if defined(CONFIG_MTD_M25P80) { /* The modalias must be the same as spi device driver name */ .modalias = "m25p80", @@ -430,14 +433,12 @@ static struct spi_board_info m25p32_spi0_board_info[] __initdata = { .chip_select = 0, .platform_data = &m25p32_spi_flash_data, }, -#endif }; static void spi_device_init(void) { spi_register_board_info(m25p32_spi0_board_info, ARRAY_SIZE(m25p32_spi0_board_info)); } -#else static struct mtd_partition mxc_nor_partitions[] = { { .name = "Bootloader", @@ -487,7 +488,6 @@ static void mx6q_setup_weimcs(void) __raw_writel(0x1C022000, nor_reg + 0x00000008); __raw_writel(0x0804a240, nor_reg + 0x00000010); } -#endif static int max7310_1_setup(struct i2c_client *client, unsigned gpio_base, unsigned ngpio, @@ -546,6 +546,9 @@ static int max7310_u39_setup(struct i2c_client *client, int n; + if (uart3_en) + max7310_gpio_value[4] = 1; + for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) { gpio_request(gpio_base + n, "MAX7310 U39 GPIO Expander"); if (max7310_gpio_value[n] < 0) @@ -615,6 +618,14 @@ static void adv7180_pwdn(int pwdn) gpio_free(SABREAUTO_VIDEOIN_PWR); } +static void mx6q_csi0_io_init(void) +{ + if (cpu_is_mx6q()) + mxc_iomux_set_gpr_register(1, 19, 1, 1); + else if (cpu_is_mx6dl()) + mxc_iomux_set_gpr_register(13, 0, 3, 4); +} + static struct fsl_mxc_tvin_platform_data adv7180_data = { .dvddio_reg = NULL, .dvdd_reg = NULL, @@ -623,6 +634,18 @@ static struct fsl_mxc_tvin_platform_data adv7180_data = { .pwdn = adv7180_pwdn, .reset = NULL, .cvbs = true, + .io_init = mx6q_csi0_io_init, +}; + +static struct fsl_mxc_tvin_platform_data adv7280_data = { + .dvddio_reg = NULL, + .dvdd_reg = NULL, + .avdd_reg = NULL, + .pvdd_reg = NULL, + .pwdn = NULL, + .cvbs = true, + /* csi slave reg address */ + .csi_tx_addr = 0x51, }; static struct imxi2c_platform_data mx6q_sabreauto_i2c2_data = { @@ -663,6 +686,11 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { .platform_data = &ls_data, }, { + I2C_BOARD_INFO("mag3110", 0x0e), + .irq = gpio_to_irq(SABREAUTO_eCOMPASS_INT), + .platform_data = (void *)&mag3110_position, + }, + { I2C_BOARD_INFO("mma8451", 0x1c), .platform_data = (void *)&mma8451_position, }, @@ -679,6 +707,9 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { .platform_data = (void *)&cs42888_data, }, { I2C_BOARD_INFO("si4763_i2c", 0x63), + }, { + I2C_BOARD_INFO("adv7280", 0x21), + .platform_data = (void *)&adv7280_data, }, }; @@ -1307,14 +1338,6 @@ static int __init early_enable_can0(char *p) } early_param("can0", early_enable_can0); -static inline void __init mx6q_csi0_io_init(void) -{ - if (cpu_is_mx6q()) - mxc_iomux_set_gpr_register(1, 19, 1, 1); - else if (cpu_is_mx6dl()) - mxc_iomux_set_gpr_register(13, 0, 3, 4); -} - static struct mxc_spdif_platform_data mxc_spdif_data = { .spdif_tx = 0, /* disable tx */ .spdif_rx = 1, /* enable rx */ @@ -1358,6 +1381,7 @@ static void __init mx6_board_init(void) iomux_v3_cfg_t *tuner_pads = NULL; iomux_v3_cfg_t *spinor_pads = NULL; iomux_v3_cfg_t *weimnor_pads = NULL; + iomux_v3_cfg_t *bluetooth_pads = NULL; iomux_v3_cfg_t *extra_pads = NULL; int common_pads_cnt; @@ -1368,6 +1392,7 @@ static void __init mx6_board_init(void) int tuner_pads_cnt; int spinor_pads_cnt; int weimnor_pads_cnt; + int bluetooth_pads_cnt; int extra_pads_cnt; if (cpu_is_mx6q()) { @@ -1378,6 +1403,7 @@ static void __init mx6_board_init(void) tuner_pads = mx6q_tuner_pads; spinor_pads = mx6q_spinor_pads; weimnor_pads = mx6q_weimnor_pads; + bluetooth_pads = mx6q_bluetooth_pads; common_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_pads); can0_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can0_pads); @@ -1386,6 +1412,7 @@ static void __init mx6_board_init(void) tuner_pads_cnt = ARRAY_SIZE(mx6q_tuner_pads); spinor_pads_cnt = ARRAY_SIZE(mx6q_spinor_pads); weimnor_pads_cnt = ARRAY_SIZE(mx6q_weimnor_pads); + bluetooth_pads_cnt = ARRAY_SIZE(mx6q_bluetooth_pads); if (board_is_mx6_reva()) { i2c3_pads = mx6q_i2c3_pads_rev_a; i2c3_pads_cnt = ARRAY_SIZE(mx6q_i2c3_pads_rev_a); @@ -1407,6 +1434,7 @@ static void __init mx6_board_init(void) tuner_pads = mx6dl_tuner_pads; spinor_pads = mx6dl_spinor_pads; weimnor_pads = mx6dl_weimnor_pads; + bluetooth_pads = mx6dl_bluetooth_pads; common_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_pads); can0_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can0_pads); @@ -1415,6 +1443,7 @@ static void __init mx6_board_init(void) tuner_pads_cnt = ARRAY_SIZE(mx6dl_tuner_pads); spinor_pads_cnt = ARRAY_SIZE(mx6dl_spinor_pads); weimnor_pads_cnt = ARRAY_SIZE(mx6dl_weimnor_pads); + bluetooth_pads_cnt = ARRAY_SIZE(mx6dl_bluetooth_pads); if (board_is_mx6_reva()) { i2c3_pads = mx6dl_i2c3_pads_rev_a; @@ -1449,6 +1478,11 @@ static void __init mx6_board_init(void) mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt); } + if (uart3_en) { + BUG_ON(!bluetooth_pads); + mxc_iomux_v3_setup_multiple_pads(bluetooth_pads, + bluetooth_pads_cnt); + } } if (can0_enable) { @@ -1554,12 +1588,12 @@ static void __init mx6_board_init(void) } /* SPI */ imx6q_add_ecspi(0, &mx6q_sabreauto_spi_data); -#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) - spi_device_init(); -#else - mx6q_setup_weimcs(); - platform_device_register(&physmap_flash_device); -#endif + if (spinor_en) + spi_device_init(); + else if (weimnor_en) { + mx6q_setup_weimcs(); + platform_device_register(&physmap_flash_device); + } imx6q_add_mxc_hdmi(&hdmi_data); imx6q_add_anatop_thermal_imx(1, &mx6q_sabreauto_anatop_thermal_data); @@ -1584,9 +1618,6 @@ static void __init mx6_board_init(void) imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); imx6q_add_asrc(&imx_asrc_data); - if (!mipi_sensor) - mx6q_csi0_io_init(); - /* DISP0 Detect */ gpio_request(SABREAUTO_DISP0_DET_INT, "disp0-detect"); gpio_direction_input(SABREAUTO_DISP0_DET_INT); @@ -1610,7 +1641,7 @@ static void __init mx6_board_init(void) imx6q_add_viim(); imx6q_add_imx2_wdt(0, NULL); imx6q_add_dma(); - if (!uart3_en) + if (!uart3_en && !weimnor_en) imx6q_add_gpmi(&mx6q_gpmi_nand_platform_data); imx6q_add_dvfs_core(&sabreauto_dvfscore_data); diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h index 9b5af3c2a68c..b1e2b9eec10b 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h @@ -172,6 +172,9 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = { /* DISP0 RESET */ MX6Q_PAD_EIM_WAIT__GPIO_5_0, + /* eCompass int */ + MX6Q_PAD_EIM_EB1__GPIO_2_29, + /* SPDIF */ MX6Q_PAD_KEY_COL3__SPDIF_IN1, @@ -188,9 +191,7 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = { MX6Q_PAD_GPIO_8__UART2_RXD, MX6Q_PAD_SD4_DAT6__UART2_CTS, MX6Q_PAD_SD4_DAT5__UART2_RTS, - /* UART 3 */ - MX6Q_PAD_SD4_CLK__UART3_TXD, - MX6Q_PAD_SD4_CMD__UART3_RXD, + /*USBs OC pin */ MX6Q_PAD_EIM_WAIT__GPIO_5_0, /*HOST1_OC*/ MX6Q_PAD_SD4_DAT0__GPIO_2_8, /*OTG_OC*/ @@ -254,8 +255,6 @@ static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = { MX6Q_PAD_NANDF_ALE__RAWNAND_ALE, MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N, MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N, - MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N, - MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N, MX6Q_PAD_NANDF_RB0__RAWNAND_READY0, MX6Q_PAD_SD4_DAT0__RAWNAND_DQS, MX6Q_PAD_NANDF_D0__RAWNAND_D0, @@ -298,6 +297,15 @@ static iomux_v3_cfg_t mx6q_spinor_pads[] __initdata = { MX6Q_PAD_EIM_D19__GPIO_3_19, }; +/*Bluetooth is conflicted with GMPI and NOR chips*/ +static iomux_v3_cfg_t mx6q_bluetooth_pads[] __initdata = { + /* UART 3 */ + MX6Q_PAD_SD4_CLK__UART3_RXD, + MX6Q_PAD_SD4_CMD__UART3_TXD, + MX6Q_PAD_EIM_D30__UART3_CTS, + MX6Q_PAD_EIM_EB3__UART3_RTS, +}; + static iomux_v3_cfg_t mx6q_weimnor_pads[] __initdata = { /* Parallel NOR */ MX6Q_PAD_EIM_OE__WEIM_WEIM_OE, diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c index 2959d0de6263..c69fe8e35217 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.c +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c @@ -75,6 +75,8 @@ static int spdc_sel; static int max17135_regulator_init(struct max17135 *max17135); static struct clk *extern_audio_root; +static void mx6sl_suspend_enter(void); +static void mx6sl_suspend_exit(void); extern char *gp_reg_id; extern char *soc_reg_id; @@ -623,7 +625,6 @@ static inline void mx6_arm2_init_uart(void) static int mx6sl_arm2_fec_phy_init(struct phy_device *phydev) { int val; - /* power on FEC phy and reset phy */ gpio_request(MX6_BRD_FEC_PWR_EN, "fec-pwr"); gpio_direction_output(MX6_BRD_FEC_PWR_EN, 0); @@ -636,7 +637,6 @@ static int mx6sl_arm2_fec_phy_init(struct phy_device *phydev) if (val & BMCR_PDOWN) { phy_write(phydev, 0x0, (val & ~BMCR_PDOWN)); } - return 0; } @@ -728,8 +728,6 @@ static void epdc_enable_pins(void) static void epdc_disable_pins(void) { - /* Configure MUX settings for EPDC pins to - * GPIO and drive to 0. */ mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_epdc_disable_pads, \ ARRAY_SIZE(mx6sl_brd_epdc_disable_pads)); @@ -970,7 +968,7 @@ static void spdc_enable_pins(void) static void spdc_disable_pins(void) { - /* Configure MUX settings for SPDC pins to + /* Configure MUX settings for EPDC pins to * GPIO and drive to 0. */ mxc_iomux_v3_setup_multiple_pads(mx6sl_brd_spdc_disable_pads, \ ARRAY_SIZE(mx6sl_brd_spdc_disable_pads)); @@ -1120,6 +1118,12 @@ static struct platform_device lcd_wvga_device = { .name = "lcd_seiko", }; +static const struct pm_platform_data mx6sl_arm2_pm_data __initconst = { + .name = "imx_pm", + .suspend_enter = mx6sl_suspend_enter, + .suspend_exit = mx6sl_suspend_exit, +}; + static int mx6sl_arm2_keymap[] = { KEY(0, 0, KEY_SELECT), KEY(0, 1, KEY_BACK), @@ -1178,6 +1182,33 @@ static void mx6_snvs_poweroff(void) writel(value | 0x60, mx6_snvs_base + SNVS_LPCR); } +static void mx6sl_suspend_enter() +{ + iomux_v3_cfg_t *p = suspend_enter_pads; + int i; + + /* Set PADCTRL to 0 for all IOMUX. */ + for (i = 0; i < ARRAY_SIZE(suspend_enter_pads); i++) { + suspend_exit_pads[i] = *p; + *p &= ~MUX_PAD_CTRL_MASK; + /* Enable the Pull down and the keeper + * Set the drive strength to 0. + */ + *p |= ((u64)0x3000 << MUX_PAD_CTRL_SHIFT); + p++; + } + mxc_iomux_v3_get_multiple_pads(suspend_exit_pads, + ARRAY_SIZE(suspend_exit_pads)); + mxc_iomux_v3_setup_multiple_pads(suspend_enter_pads, + ARRAY_SIZE(suspend_enter_pads)); +} + +static void mx6sl_suspend_exit() +{ + mxc_iomux_v3_setup_multiple_pads(suspend_exit_pads, + ARRAY_SIZE(suspend_exit_pads)); +} + /*! * Board specific initialization. */ @@ -1267,6 +1298,7 @@ static void __init mx6_arm2_init(void) imx6q_add_perfmon(0); imx6q_add_perfmon(1); imx6q_add_perfmon(2); + imx6q_add_pm_imx(0, &mx6sl_arm2_pm_data); pm_power_off = mx6_snvs_poweroff; } diff --git a/arch/arm/mach-mx6/board-mx6sl_common.h b/arch/arm/mach-mx6/board-mx6sl_common.h index 4a04cbea0694..a6e5e909c6a9 100644 --- a/arch/arm/mach-mx6/board-mx6sl_common.h +++ b/arch/arm/mach-mx6/board-mx6sl_common.h @@ -389,41 +389,116 @@ static iomux_v3_cfg_t mx6sl_brd_spdc_disable_pads[] = { MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, }; -static iomux_v3_cfg_t mx6sl_brd_csi_enable_pads[] = { - MX6SL_PAD_EPDC_GDRL__CSI_MCLK, - MX6SL_PAD_EPDC_SDCE3__I2C3_SDA, - MX6SL_PAD_EPDC_SDCE2__I2C3_SCL, - MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK, - MX6SL_PAD_EPDC_GDSP__CSI_VSYNC, - MX6SL_PAD_EPDC_GDOE__CSI_HSYNC, - MX6SL_PAD_EPDC_SDLE__CSI_D_9, - MX6SL_PAD_EPDC_SDCLK__CSI_D_8, - MX6SL_PAD_EPDC_D7__CSI_D_7, - MX6SL_PAD_EPDC_D6__CSI_D_6, - MX6SL_PAD_EPDC_D5__CSI_D_5, - MX6SL_PAD_EPDC_D4__CSI_D_4, - MX6SL_PAD_EPDC_D3__CSI_D_3, - MX6SL_PAD_EPDC_D2__CSI_D_2, - MX6SL_PAD_EPDC_D1__CSI_D_1, - MX6SL_PAD_EPDC_D0__CSI_D_0, - - MX6SL_PAD_EPDC_SDSHR__GPIO_1_26, /* CMOS_RESET_B GPIO */ - MX6SL_PAD_EPDC_SDOE__GPIO_1_25, /* CMOS_PWDN GPIO */ -}; - static iomux_v3_cfg_t mx6sl_brd_elan_pads[] = { MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10, /* INT */ MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9, /* CE */ MX6SL_PAD_KEY_COL6__GPIO_4_4, /* RST */ }; - /* uart2 pins */ -static iomux_v3_cfg_t mx6sl_uart2_pads[] = { - MX6SL_PAD_SD2_DAT5__UART2_TXD, - MX6SL_PAD_SD2_DAT4__UART2_RXD, - MX6SL_PAD_SD2_DAT6__UART2_RTS, - MX6SL_PAD_SD2_DAT7__UART2_CTS, + +static iomux_v3_cfg_t suspend_enter_pads[] = { + /* Audio pads. */ + MX6SL_PAD_AUD_MCLK__GPIO_1_6, + MX6SL_PAD_AUD_RXC__GPIO_1_1, + MX6SL_PAD_AUD_RXD__GPIO_1_2, + MX6SL_PAD_AUD_RXFS__GPIO_1_0, + MX6SL_PAD_AUD_TXC__GPIO_1_3, + MX6SL_PAD_AUD_TXD__GPIO_1_5, + MX6SL_PAD_AUD_TXFS__GPIO_1_4, + /* ECSPI pads. */ + MX6SL_PAD_ECSPI1_MISO__GPIO_4_10, + MX6SL_PAD_ECSPI1_MOSI__GPIO_4_9, + MX6SL_PAD_ECSPI1_SCLK__GPIO_4_8, + MX6SL_PAD_ECSPI1_SS0__GPIO_4_11, + MX6SL_PAD_ECSPI2_SCLK__GPIO_4_12, + /* FEC pad*/ + MX6SL_PAD_FEC_CRS_DV__GPIO_4_25, + MX6SL_PAD_FEC_MDC__GPIO_4_23, + MX6SL_PAD_FEC_MDIO__GPIO_4_20, + MX6SL_PAD_FEC_REF_CLK__GPIO_4_26, + MX6SL_PAD_FEC_RXD0__GPIO_4_17, + MX6SL_PAD_FEC_RXD1__GPIO_4_18, + MX6SL_PAD_FEC_TXD0__GPIO_4_24, + MX6SL_PAD_FEC_TXD1__GPIO_4_16, + MX6SL_PAD_FEC_TX_CLK__GPIO_4_21, + MX6SL_PAD_FEC_TX_EN__GPIO_4_22, + /* I2C pads */ + MX6SL_PAD_I2C1_SCL__GPIO_3_12, + MX6SL_PAD_I2C1_SDA__GPIO_3_13, + MX6SL_PAD_I2C2_SCL__GPIO_3_14, + MX6SL_PAD_I2C2_SDA__GPIO_3_15, + /* LCD pads*/ + MX6SL_PAD_LCD_CLK__GPIO_2_15, + MX6SL_PAD_LCD_DAT0__GPIO_2_20, + MX6SL_PAD_LCD_DAT1__GPIO_2_21, + MX6SL_PAD_LCD_DAT2__GPIO_2_22, + MX6SL_PAD_LCD_DAT3__GPIO_2_23, + MX6SL_PAD_LCD_DAT4__GPIO_2_24, + MX6SL_PAD_LCD_DAT5__GPIO_2_25, + MX6SL_PAD_LCD_DAT10__GPIO_2_30, + MX6SL_PAD_LCD_DAT11__GPIO_2_31, + MX6SL_PAD_LCD_DAT12__GPIO_3_0, + MX6SL_PAD_LCD_DAT13__GPIO_3_1, + MX6SL_PAD_LCD_DAT14__GPIO_3_2, + MX6SL_PAD_LCD_DAT15__GPIO_3_3, + MX6SL_PAD_LCD_DAT16__GPIO_3_4, + MX6SL_PAD_LCD_DAT17__GPIO_3_5, + MX6SL_PAD_LCD_DAT18__GPIO_3_6, + MX6SL_PAD_LCD_DAT19__GPIO_3_7, + MX6SL_PAD_LCD_DAT20__GPIO_3_8, + MX6SL_PAD_LCD_DAT21__GPIO_3_9, + MX6SL_PAD_LCD_DAT22__GPIO_3_10, + MX6SL_PAD_LCD_DAT23__GPIO_3_11, + /* PWM pads */ + MX6SL_PAD_PWM1__GPIO_3_23, + /* SD pads. */ + MX6SL_PAD_SD1_CLK__GPIO_5_15, + MX6SL_PAD_SD1_CMD__GPIO_5_14, + MX6SL_PAD_SD1_DAT0__GPIO_5_11, + MX6SL_PAD_SD1_DAT1__GPIO_5_8, + MX6SL_PAD_SD1_DAT2__GPIO_5_13, + MX6SL_PAD_SD1_DAT3__GPIO_5_6, + MX6SL_PAD_SD1_DAT4__GPIO_5_12, + MX6SL_PAD_SD1_DAT5__GPIO_5_9, + MX6SL_PAD_SD1_DAT6__GPIO_5_7, + MX6SL_PAD_SD1_DAT7__GPIO_5_10, + MX6SL_PAD_SD2_CLK__GPIO_5_5, + MX6SL_PAD_SD2_CMD__GPIO_5_4, + MX6SL_PAD_SD2_DAT0__GPIO_5_1, + MX6SL_PAD_SD2_DAT1__GPIO_4_30, + MX6SL_PAD_SD2_DAT2__GPIO_5_3, + MX6SL_PAD_SD2_DAT3__GPIO_4_28, + MX6SL_PAD_SD2_DAT4__GPIO_5_2, + MX6SL_PAD_SD2_DAT5__GPIO_4_31, + MX6SL_PAD_SD2_DAT6__GPIO_4_29, + MX6SL_PAD_SD2_DAT7__GPIO_5_0, + MX6SL_PAD_SD3_CLK__GPIO_5_18, + MX6SL_PAD_SD3_CMD__GPIO_5_21, + MX6SL_PAD_SD3_DAT0__GPIO_5_19, + MX6SL_PAD_SD3_DAT1__GPIO_5_20, + MX6SL_PAD_SD3_DAT2__GPIO_5_16, + MX6SL_PAD_SD3_DAT3__GPIO_5_17, + /* USBOTG ID pin */ + MX6SL_PAD_EPDC_PWRCOM__GPIO_2_11, + MX6SL_PAD_HSIC_STROBE__GPIO_3_20, + MX6SL_PAD_HSIC_DAT__GPIO_3_19, + /* Key row/column */ + MX6SL_PAD_KEY_COL0__GPIO_3_24, + MX6SL_PAD_KEY_COL1__GPIO_3_26, + MX6SL_PAD_KEY_COL2__GPIO_3_28, + MX6SL_PAD_KEY_COL3__GPIO_3_30, + MX6SL_PAD_KEY_COL6__GPIO_4_4, + MX6SL_PAD_KEY_COL7__GPIO_4_6, + MX6SL_PAD_KEY_ROW0__GPIO_3_25, + MX6SL_PAD_KEY_ROW1__GPIO_3_27, + MX6SL_PAD_KEY_ROW2__GPIO_3_29, + MX6SL_PAD_KEY_ROW3__GPIO_3_31, + MX6SL_PAD_KEY_ROW4__GPIO_4_1, + MX6SL_PAD_KEY_ROW5__GPIO_4_3, + MX6SL_PAD_KEY_ROW6__GPIO_4_5, }; +static iomux_v3_cfg_t suspend_exit_pads[ARRAY_SIZE(suspend_enter_pads)]; + #define MX6SL_USDHC_8BIT_PAD_SETTING(id, speed) \ mx6sl_sd##id##_##speed##mhz[] = { \ MX6SL_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ, \ diff --git a/arch/arm/mach-mx6/board-mx6sl_evk.c b/arch/arm/mach-mx6/board-mx6sl_evk.c index 9bdd6c197e5c..47e8a8954c7d 100644 --- a/arch/arm/mach-mx6/board-mx6sl_evk.c +++ b/arch/arm/mach-mx6/board-mx6sl_evk.c @@ -77,6 +77,9 @@ static int spdc_sel; static int max17135_regulator_init(struct max17135 *max17135); +static void mx6sl_evk_suspend_enter(void); +static void mx6sl_evk_suspend_exit(void); + struct clk *extern_audio_root; extern char *gp_reg_id; @@ -86,12 +89,48 @@ extern int __init mx6sl_evk_init_pfuze100(u32 int_gpio); static int csi_enabled; +static iomux_v3_cfg_t mx6sl_brd_csi_enable_pads[] = { + MX6SL_PAD_EPDC_GDRL__CSI_MCLK, + MX6SL_PAD_EPDC_SDCE3__I2C3_SDA, + MX6SL_PAD_EPDC_SDCE2__I2C3_SCL, + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK, + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC, + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC, + MX6SL_PAD_EPDC_SDLE__CSI_D_9, + MX6SL_PAD_EPDC_SDCLK__CSI_D_8, + MX6SL_PAD_EPDC_D7__CSI_D_7, + MX6SL_PAD_EPDC_D6__CSI_D_6, + MX6SL_PAD_EPDC_D5__CSI_D_5, + MX6SL_PAD_EPDC_D4__CSI_D_4, + MX6SL_PAD_EPDC_D3__CSI_D_3, + MX6SL_PAD_EPDC_D2__CSI_D_2, + MX6SL_PAD_EPDC_D1__CSI_D_1, + MX6SL_PAD_EPDC_D0__CSI_D_0, + + MX6SL_PAD_EPDC_SDSHR__GPIO_1_26, /* CMOS_RESET_B GPIO */ + MX6SL_PAD_EPDC_SDOE__GPIO_1_25, /* CMOS_PWDN GPIO */ +}; + +/* uart2 pins */ +static iomux_v3_cfg_t mx6sl_uart2_pads[] = { + MX6SL_PAD_SD2_DAT5__UART2_TXD, + MX6SL_PAD_SD2_DAT4__UART2_RXD, + MX6SL_PAD_SD2_DAT6__UART2_RTS, + MX6SL_PAD_SD2_DAT7__UART2_CTS, +}; + enum sd_pad_mode { SD_PAD_MODE_LOW_SPEED, SD_PAD_MODE_MED_SPEED, SD_PAD_MODE_HIGH_SPEED, }; +static const struct pm_platform_data mx6sl_evk_pm_data __initconst = { + .name = "imx_pm", + .suspend_enter = mx6sl_evk_suspend_enter, + .suspend_exit = mx6sl_evk_suspend_exit, +}; + static int __init csi_setup(char *__unused) { csi_enabled = 1; @@ -1381,6 +1420,35 @@ static void __init uart2_init(void) ARRAY_SIZE(mx6sl_uart2_pads)); imx6sl_add_imx_uart(1, &mx6sl_evk_uart1_data); } + +static void mx6sl_evk_suspend_enter() +{ + iomux_v3_cfg_t *p = suspend_enter_pads; + int i; + + /* Set PADCTRL to 0 for all IOMUX. */ + for (i = 0; i < ARRAY_SIZE(suspend_enter_pads); i++) { + suspend_exit_pads[i] = *p; + *p &= ~MUX_PAD_CTRL_MASK; + /* Enable the Pull down and the keeper + * Set the drive strength to 0. + */ + *p |= ((u64)0x3000 << MUX_PAD_CTRL_SHIFT); + p++; + } + mxc_iomux_v3_get_multiple_pads(suspend_exit_pads, + ARRAY_SIZE(suspend_exit_pads)); + mxc_iomux_v3_setup_multiple_pads(suspend_enter_pads, + ARRAY_SIZE(suspend_enter_pads)); + +} + +static void mx6sl_evk_suspend_exit() +{ + mxc_iomux_v3_setup_multiple_pads(suspend_exit_pads, + ARRAY_SIZE(suspend_exit_pads)); +} + /*! * Board specific initialization. */ @@ -1509,6 +1577,7 @@ static void __init mx6_evk_init(void) /* Register charger chips */ platform_device_register(&evk_max8903_charger_1); pm_power_off = mx6_snvs_poweroff; + imx6q_add_pm_imx(0, &mx6sl_evk_pm_data); } extern void __iomem *twd_base; diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h index b752faae33ba..31c3a6182b93 100644 --- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h +++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h @@ -188,9 +188,7 @@ static iomux_v3_cfg_t mx6dl_sabreauto_pads[] = { MX6DL_PAD_GPIO_8__UART2_RXD, MX6DL_PAD_SD4_DAT6__UART2_CTS, MX6DL_PAD_SD4_DAT5__UART2_RTS, - /* UART 3 */ - MX6DL_PAD_SD4_CLK__UART3_TXD, - MX6DL_PAD_SD4_CMD__UART3_RXD, + /*USBs OC pin */ MX6DL_PAD_EIM_WAIT__GPIO_5_0, /*HOST1_OC*/ MX6DL_PAD_SD4_DAT0__GPIO_2_8, /*OTG_OC*/ @@ -254,8 +252,6 @@ static iomux_v3_cfg_t mx6dl_gpmi_nand[] __initdata = { MX6DL_PAD_NANDF_ALE__RAWNAND_ALE, MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N, MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N, - MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N, - MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N, MX6DL_PAD_NANDF_RB0__RAWNAND_READY0, MX6DL_PAD_SD4_DAT0__RAWNAND_DQS, MX6DL_PAD_NANDF_D0__RAWNAND_D0, @@ -299,6 +295,15 @@ static iomux_v3_cfg_t mx6dl_spinor_pads[] __initdata = { MX6DL_PAD_EIM_D19__GPIO_3_19, }; +/*Bluetooth is conflicted with GMPI and NOR chips*/ +static iomux_v3_cfg_t mx6dl_bluetooth_pads[] __initdata = { + /* UART 3 */ + MX6DL_PAD_SD4_CLK__UART3_RXD, + MX6DL_PAD_SD4_CMD__UART3_TXD, + MX6DL_PAD_EIM_D30__UART3_CTS, + MX6DL_PAD_EIM_EB3__UART3_RTS, +}; + static iomux_v3_cfg_t mx6dl_weimnor_pads[] __initdata = { /* Parallel NOR */ MX6DL_PAD_EIM_OE__WEIM_WEIM_OE, diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 0c05c37f81d5..1a8636e6eb45 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5344,8 +5344,13 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_debug_register(lookups[i].clk); } - /* Lower the ipg_perclk frequency to 6MHz. */ - clk_set_rate(&ipg_perclk, 6000000); + /* Lower the ipg_perclk frequency to 22MHz. + * I2C needs a minimum of 12.8MHz as its source + * to acheive 400KHz speed. IPG_PERCLK sources + * I2C. 22MHz when divided by the I2C divider gives the + * freq closest to 400KHz. + */ + clk_set_rate(&ipg_perclk, 22000000); /* Timer needs to be initialized first as the * the WAIT routines use GPT counter as diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index a18427c51515..961e7ee829ff 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -101,7 +101,6 @@ DEFINE_SPINLOCK(mx6sl_clk_lock); u32 gpt_ticks; \ u32 gpt_cnt; \ u32 reg; \ - unsigned long flags; \ int result = 1; \ gpt_rate = clk_get_rate(&gpt_clk[0]); \ gpt_ticks = timeout / (1000000000 / gpt_rate); \ @@ -4004,11 +4003,14 @@ int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc, * should be from OSC24M */ clk_set_parent(&ipg_perclk, &osc_clk); - /* Need to set IPG_PERCLK to 3MHz, so that we can - * satisfy the 2.5:1 AHB:IPG_PERCLK ratio. Since AHB - * can be dropped to as low as 8MHz in low power mode. + + /*IPG_PERCLK sources I2C. + * I2C needs a minimum of 12.8MHz as its source + * to acheive 400KHz speed. + * Hence set ipg_perclk to 24MHz. */ - clk_set_rate(&ipg_perclk, 3000000); + + clk_set_rate(&ipg_perclk, 24000000); gpt_clk[0].parent = &ipg_perclk; gpt_clk[0].get_rate = NULL; diff --git a/arch/arm/mach-mx6/cpu_regulator-mx6.c b/arch/arm/mach-mx6/cpu_regulator-mx6.c index 5019f8bedff2..8eb976d2eefd 100644 --- a/arch/arm/mach-mx6/cpu_regulator-mx6.c +++ b/arch/arm/mach-mx6/cpu_regulator-mx6.c @@ -62,7 +62,9 @@ void mx6_cpu_regulator_init(void) { int cpu; u32 curr_cpu = 0; - +#ifndef CONFIG_SMP + unsigned long old_loops_per_jiffy; +#endif external_pureg = 0; cpu_regulator = regulator_get(NULL, gp_reg_id); if (IS_ERR(cpu_regulator)) @@ -90,7 +92,7 @@ void mx6_cpu_regulator_init(void) curr_cpu / 1000, clk_get_rate(cpu_clk) / 1000); #else - u32 old_loops_per_jiffy = loops_per_jiffy; + old_loops_per_jiffy = loops_per_jiffy; loops_per_jiffy = mx6_cpu_jiffies(old_loops_per_jiffy, diff --git a/arch/arm/mach-mx6/mx6_anatop_regulator.c b/arch/arm/mach-mx6/mx6_anatop_regulator.c index f2c2ebf600b3..9599a5439e54 100644 --- a/arch/arm/mach-mx6/mx6_anatop_regulator.c +++ b/arch/arm/mach-mx6/mx6_anatop_regulator.c @@ -273,6 +273,24 @@ static int is_enabled(struct anatop_regulator *sreg) { return 1; } +static int vdd3p0_enable(struct anatop_regulator *sreg) +{ + __raw_writel(BM_ANADIG_REG_3P0_ENABLE_LINREG, + sreg->rdata->control_reg+4); + return 0; +} + +static int vdd3p0_disable(struct anatop_regulator *sreg) +{ + __raw_writel(BM_ANADIG_REG_3P0_ENABLE_LINREG, + sreg->rdata->control_reg+8); + return 0; +} + +static int vdd3p0_is_enabled(struct anatop_regulator *sreg) +{ + return !!(__raw_readl(sreg->rdata->control_reg) & BM_ANADIG_REG_3P0_ENABLE_LINREG); +} static struct anatop_regulator_data vddpu_data = { .name = "vddpu", @@ -353,15 +371,15 @@ static struct anatop_regulator_data vdd3p0_data = { .name = "vdd3p0", .set_voltage = set_voltage, .get_voltage = get_voltage, - .enable = enable, - .disable = disable, - .is_enabled = is_enabled, + .enable = vdd3p0_enable, + .disable = vdd3p0_disable, + .is_enabled = vdd3p0_is_enabled, .control_reg = (u32)(MXC_PLL_BASE + HW_ANADIG_REG_3P0), .vol_bit_shift = 8, .vol_bit_mask = 0x1F, - .min_bit_val = 7, - .min_voltage = 2800000, - .max_voltage = 3150000, + .min_bit_val = 0, + .min_voltage = 2625000, + .max_voltage = 3400000, }; /* CPU */ @@ -386,6 +404,13 @@ static struct regulator_consumer_supply vddsoc_consumers[] = { }, }; +/* USB phy 3P0 */ +static struct regulator_consumer_supply vdd3p0_consumers[] = { + { + .supply = "cpu_vdd3p0", + }, +}; + static struct regulator_init_data vddpu_init = { .constraints = { .name = "vddpu", @@ -467,16 +492,17 @@ static struct regulator_init_data vdd1p1_init = { static struct regulator_init_data vdd3p0_init = { .constraints = { .name = "vdd3p0", - .min_uV = 2800000, - .max_uV = 3150000, + .min_uV = 2625000, + .max_uV = 3400000, .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE, - .always_on = 1, + REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS, + .always_on = 0, }, - .num_consumer_supplies = 0, - .consumer_supplies = NULL, + .num_consumer_supplies = ARRAY_SIZE(vdd3p0_consumers), + .consumer_supplies = &vdd3p0_consumers[0], }; static struct anatop_regulator vddpu_reg = { diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S index 1987581e56aa..f712700a8e68 100644 --- a/arch/arm/mach-mx6/mx6_suspend.S +++ b/arch/arm/mach-mx6/mx6_suspend.S @@ -233,6 +233,11 @@ wait_for_pll_lock: bic r6, r6, #0x2000000 str r6, [r3, #0x14] +periph_clk_switch1: + ldr r6, [r3, #0x48] + cmp r6, #0 + bne periph_clk_switch1 + /* Set the dividers to default value. */ ldr r6, [r3, #0x14] bic r6, r6, #0x70000 @@ -241,14 +246,9 @@ wait_for_pll_lock: str r6, [r3, #0x14] ahb_podf1: - ldr r0, [r3, #0x48] - cmp r0, #0 - bne ahb_podf1 - -periph_clk_switch1: ldr r6, [r3, #0x48] cmp r6, #0 - bne periph_clk_switch1 + bne ahb_podf1 /* Move MMDC back to PLL2_PFD2_400 */ ldr r6, [r3, #0x14] @@ -262,7 +262,7 @@ mmdc_loop2: /* Set DDR clock to divide by 1. */ ldr r6, [r3, #0x14] - bic r6, r0, #0x38 + bic r6, r6, #0x38 str r6, [r3, #0x14] mmdc_div1: @@ -1099,6 +1099,12 @@ set ddr iomux to low power mode ldr r1, =CCM_BASE_ADDR add r1, r1, #PERIPBASE_VIRT ldr r0, [r1] + ldr r1, =GPC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] + ldr r1, =CCM_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] #ifdef CONFIG_MX6_INTER_LDO_BYPASS ldr r1, =ANATOP_BASE_ADDR add r1, r1, #PERIPBASE_VIRT @@ -1173,6 +1179,66 @@ save resume pointer into SRC_GPR1 add r1, r1, #PERIPBASE_VIRT str r3, [r1, #SRC_GPR1_OFFSET] + /* Mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r3, =GPC_BASE_ADDR + add r3, r3, #PERIPBASE_VIRT + ldr r4, [r3, #0x08] + ldr r5, [r3, #0x0c] + ldr r6, [r3, #0x10] + ldr r7, [r3, #0x14] + + ldr r8, =0xffffffff + str r8, [r3, #0x08] + str r8, [r3, #0x0c] + str r8, [r3, #0x10] + str r8, [r3, #0x14] + + /* Enable the RBC bypass counter here + * to hold off the interrupts. + * RBC counter = 32 (1ms) + * Minimum RBC delay should be + * 400us for the analog LDOs to + * power down. + */ + ldr r1, =CCM_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r8, [r1, #0x0] + ldr r0, =0x7E00000 + bic r8, r8, r0 + ldr r0, =0x4000000 + orr r8, r8, r0 + str r8, [r1, #0x0] + + /* Enable the counter. */ + ldr r8, [r1, #0x0] + orr r8, r8, #0x8000000 + str r8, [r1, #0x0] + + /* Unmask all the GPC interrupts. */ + str r4, [r3, #0x08] + str r5, [r3, #0x0c] + str r6, [r3, #0x10] + str r7, [r3, #0x14] + + /* Now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * This delay is required to ensure that + * the RBC counter can start counting in case an + * interrupt is already pending or in case an interrupt + * arrives just as ARM is about to assert DSM_request. + */ + ldr r4, =2000 +rbc_loop: + sub r4, r4, #0x1 + cmp r4, #0x0 + bne rbc_loop + #ifdef CONFIG_MX6_INTER_LDO_BYPASS ldr r1, =ANATOP_BASE_ADDR add r1, r1, #PERIPBASE_VIRT diff --git a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c index 8cb4ffcc78fa..3987777d56ff 100644 --- a/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c +++ b/arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c @@ -24,7 +24,11 @@ #include <linux/gpio.h> #include <linux/regulator/machine.h> #include <linux/mfd/pfuze.h> +#include <linux/io.h> #include <mach/irqs.h> +#include "crm_regs.h" +#include "regs-anadig.h" +#include "cpu_op-mx6.h" /* * Convenience conversion. @@ -38,32 +42,21 @@ #define PFUZE100_I2C_DEVICE_NAME "pfuze100" /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) - - /*SWBST*/ -#define PFUZE100_SW1ASTANDBY 33 -#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x19) -#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1BSTANDBY 40 -#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x19) -#define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1CSTANDBY 47 -#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x19) -#define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW2STANDBY 54 -#define PFUZE100_SW2STANDBY_STBY_VAL 0x0 -#define PFUZE100_SW2STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3ASTANDBY 61 -#define PFUZE100_SW3ASTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3BSTANDBY 68 -#define PFUZE100_SW3BSTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW4STANDBY 75 -#define PFUZE100_SW4STANDBY_STBY_VAL 0 -#define PFUZE100_SW4STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SWBSTCON1 102 -#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2) -#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2) +#define PFUZE100_DEVICEID (0x0) +#define PFUZE100_REVID (0x3) +#define PFUZE100_SW1AMODE (0x23) +#define PFUZE100_SW1AVOL 32 +#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) +#define PFUZE100_SW1CVOL 46 +#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) +#define PFUZE100_SW1ACON 36 +#define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ +#define PFUZE100_SW1ACON_SPEED_M (0x3<<6) +#define PFUZE100_SW1CCON 49 +#define PFUZE100_SW1CCON_SPEED_VAL (0x1<<6) /*default */ +#define PFUZE100_SW1CCON_SPEED_M (0x3<<6) + +extern u32 arm_max_freq; static struct regulator_consumer_supply sw1a_consumers[] = { { @@ -157,7 +150,13 @@ static struct regulator_init_data sw1a_init = { .valid_modes_mask = 0, .boot_on = 1, .always_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), .consumer_supplies = sw1a_consumers, }; @@ -183,7 +182,13 @@ static struct regulator_init_data sw1c_init = { .valid_modes_mask = 0, .always_on = 1, .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers), .consumer_supplies = sw1c_consumers, }; @@ -391,20 +396,82 @@ static struct regulator_init_data vgen6_init = { static int pfuze100_init(struct mc_pfuze *pfuze) { - int ret; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY, - PFUZE100_SW1ASTANDBY_STBY_M, - PFUZE100_SW1ASTANDBY_STBY_VAL); + int ret, i; + unsigned int reg; + unsigned char value; + /*read Device ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value); + if (ret) + goto err; + if (value != 0x10) { + printk(KERN_ERR "wrong device id:%x!\n", value); + goto err; + } + + /*read Revision ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value); if (ret) goto err; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1BSTANDBY, - PFUZE100_SW1BSTANDBY_STBY_M, - PFUZE100_SW1BSTANDBY_STBY_VAL); + if (value == 0x10) { + printk(KERN_WARNING "PF100 1.0 chip found!\n"); + /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode + * except SW1C(APS) in normal and PFM mode in standby. + */ + for (i = 0; i < 7; i++) { + if (i == 2)/*SW1C*/ + value = 0xc;/*normal:APS mode;standby:PFM mode*/ + else + value = 0xd;/*normal:PWM mode;standby:PFM mode*/ + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } else { + /*set all switches APS in normal and PFM mode in standby*/ + for (i = 0; i < 7; i++) { + value = 0xc; + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } + if (arm_max_freq == CPU_AT_1_2GHz) { + /*VDDARM_IN 1.475V*/ + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL, + PFUZE100_SW1AVOL_VSEL_M, + 0x2f); + if (ret) + goto err; + /*VDDSOC_IN 1.475V*/ + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL, + PFUZE100_SW1CVOL_VSEL_M, + 0x2f); + if (ret) + goto err; + /*set VDDSOC&VDDPU to 1.25V*/ + reg = __raw_readl(ANADIG_REG_CORE); + reg &= ~BM_ANADIG_REG_CORE_REG2_TRG; + reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16); + reg &= ~BM_ANADIG_REG_CORE_REG1_TRG; + reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16); + __raw_writel(reg, ANADIG_REG_CORE); + + } + /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/ + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON, + PFUZE100_SW1ACON_SPEED_M, + PFUZE100_SW1ACON_SPEED_VAL); if (ret) goto err; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, - PFUZE100_SW1CSTANDBY_STBY_M, - PFUZE100_SW1CSTANDBY_STBY_VAL); + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON, + PFUZE100_SW1CCON_SPEED_M, + PFUZE100_SW1CCON_SPEED_VAL); if (ret) goto err; return 0; diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c index cbde44955f03..6b38bd000bc0 100644 --- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c +++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c @@ -41,36 +41,14 @@ #define PFUZE100_I2C_DEVICE_NAME "pfuze100" /* 7-bit I2C bus slave address */ -#define PFUZE100_I2C_ADDR (0x08) - /*SWBST*/ -#define PFUZE100_SW1AVOL 32 -#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) -#define PFUZE100_SW1CVOL 46 -#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) -#define PFUZE100_SW1ASTANDBY 33 -#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x19) -#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1BSTANDBY 40 -#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x19) -#define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1CSTANDBY 47 -#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x19) -#define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW2STANDBY 54 -#define PFUZE100_SW2STANDBY_STBY_VAL 0x0 -#define PFUZE100_SW2STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3ASTANDBY 61 -#define PFUZE100_SW3ASTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3BSTANDBY 68 -#define PFUZE100_SW3BSTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW4STANDBY 75 -#define PFUZE100_SW4STANDBY_STBY_VAL 0 -#define PFUZE100_SW4STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SWBSTCON1 102 -#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2) -#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2) +#define PFUZE100_I2C_ADDR (0x08) +#define PFUZE100_DEVICEID (0x0) +#define PFUZE100_REVID (0x3) +#define PFUZE100_SW1AMODE (0x23) +#define PFUZE100_SW1AVOL 32 +#define PFUZE100_SW1AVOL_VSEL_M (0x3f<<0) +#define PFUZE100_SW1CVOL 46 +#define PFUZE100_SW1CVOL_VSEL_M (0x3f<<0) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ #define PFUZE100_SW1ACON_SPEED_M (0x3<<6) @@ -166,7 +144,13 @@ static struct regulator_init_data sw1a_init = { .valid_modes_mask = 0, .boot_on = 1, .always_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, #ifdef CONFIG_MX6_INTER_LDO_BYPASS .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), @@ -195,7 +179,13 @@ static struct regulator_init_data sw1c_init = { .valid_modes_mask = 0, .always_on = 1, .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, #ifdef CONFIG_MX6_INTER_LDO_BYPASS .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers), .consumer_supplies = sw1c_consumers, @@ -399,8 +389,52 @@ static struct regulator_init_data vgen6_init = { static int pfuze100_init(struct mc_pfuze *pfuze) { - int ret; + int ret, i; unsigned int reg; + unsigned char value; + /*read Device ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value); + if (ret) + goto err; + if (value != 0x10) { + printk(KERN_ERR "wrong device id:%x!\n", value); + goto err; + } + + /*read Revision ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value); + if (ret) + goto err; + if (value == 0x10) { + printk(KERN_WARNING "PF100 1.0 chip found!\n"); + /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode + * except SW1C(APS) in normal and PFM mode in standby. + */ + for (i = 0; i < 7; i++) { + if (i == 2)/*SW1C*/ + value = 0xc;/*normal:APS mode;standby:PFM mode*/ + else + value = 0xd;/*normal:PWM mode;standby:PFM mode*/ + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } else { + /*set all switches APS in normal and PFM mode in standby*/ + for (i = 0; i < 7; i++) { + value = 0xc; + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } + if (arm_max_freq == CPU_AT_1_2GHz) { /*VDDARM_IN 1.475V*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL, @@ -423,16 +457,6 @@ static int pfuze100_init(struct mc_pfuze *pfuze) __raw_writel(reg, ANADIG_REG_CORE); } - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY, - PFUZE100_SW1ASTANDBY_STBY_M, - PFUZE100_SW1ASTANDBY_STBY_VAL); - if (ret) - goto err; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, - PFUZE100_SW1CSTANDBY_STBY_M, - PFUZE100_SW1CSTANDBY_STBY_VAL); - if (ret) - goto err; /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON, PFUZE100_SW1ACON_SPEED_M, diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c index 5cf34073bdc1..55a802b76b68 100644 --- a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c +++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c @@ -38,31 +38,9 @@ #define PFUZE100_I2C_DEVICE_NAME "pfuze100" /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) - /*SWBST*/ -#define PFUZE100_SW1ASTANDBY 33 -#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x19) /* 925mV */ -#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1BSTANDBY 40 -#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x19) /* 925mV */ -#define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1CSTANDBY 47 -#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x19) /* 925mV */ -#define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW2STANDBY 54 -#define PFUZE100_SW2STANDBY_STBY_VAL 0x0 -#define PFUZE100_SW2STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3ASTANDBY 61 -#define PFUZE100_SW3ASTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3BSTANDBY 68 -#define PFUZE100_SW3BSTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW4STANDBY 75 -#define PFUZE100_SW4STANDBY_STBY_VAL 0 -#define PFUZE100_SW4STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SWBSTCON1 102 -#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2) -#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2) +#define PFUZE100_DEVICEID (0x0) +#define PFUZE100_REVID (0x3) +#define PFUZE100_SW1AMODE (0x23) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ #define PFUZE100_SW1ACON_SPEED_M (0x3<<6) @@ -158,7 +136,13 @@ static struct regulator_init_data sw1a_init = { .valid_modes_mask = 0, .boot_on = 1, .always_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, #ifdef CONFIG_MX6_INTER_LDO_BYPASS .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), .consumer_supplies = sw1_consumers, @@ -186,7 +170,13 @@ static struct regulator_init_data sw1c_init = { .valid_modes_mask = 0, .always_on = 1, .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, #ifdef CONFIG_MX6_INTER_LDO_BYPASS .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers), .consumer_supplies = sw1c_consumers, @@ -392,17 +382,51 @@ static struct regulator_init_data vgen6_init = { static int pfuze100_init(struct mc_pfuze *pfuze) { - int ret; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY, - PFUZE100_SW1ASTANDBY_STBY_M, - PFUZE100_SW1ASTANDBY_STBY_VAL); + int ret, i; + unsigned int reg; + unsigned char value; + /*read Device ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value); if (ret) goto err; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, - PFUZE100_SW1CSTANDBY_STBY_M, - PFUZE100_SW1CSTANDBY_STBY_VAL); + if (value != 0x10) { + printk(KERN_ERR "wrong device id:%x!\n", value); + goto err; + } + + /*read Revision ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value); if (ret) goto err; + if (value == 0x10) { + printk(KERN_WARNING "PF100 1.0 chip found!\n"); + /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode + * except SW1C(APS) in normal and PFM mode in standby. + */ + for (i = 0; i < 7; i++) { + if (i == 2)/*SW1C*/ + value = 0xc;/*normal:APS mode;standby:PFM mode*/ + else + value = 0xd;/*normal:PWM mode;standby:PFM mode*/ + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } else { + /*set all switches APS in normal and PFM mode in standby*/ + for (i = 0; i < 7; i++) { + value = 0xc; + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } /*set SW1AB/SW1C DVSPEED as 25mV step each 4us,quick than 16us before.*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON, PFUZE100_SW1ACON_SPEED_M, diff --git a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c index 981d149d7aee..bfd5fafc1d1b 100644 --- a/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c +++ b/arch/arm/mach-mx6/mx6sl_evk_pmic_pfuze100.c @@ -38,31 +38,9 @@ #define PFUZE100_I2C_DEVICE_NAME "pfuze100" /* 7-bit I2C bus slave address */ #define PFUZE100_I2C_ADDR (0x08) - /*SWBST*/ -#define PFUZE100_SW1ASTANDBY 33 -#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x19) /* 925mv */ -#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1BSTANDBY 40 -#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x19) /* 925mv */ -#define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW1CSTANDBY 47 -#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x19) /* 925mv */ -#define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW2STANDBY 54 -#define PFUZE100_SW2STANDBY_STBY_VAL 0x0 -#define PFUZE100_SW2STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3ASTANDBY 61 -#define PFUZE100_SW3ASTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3ASTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW3BSTANDBY 68 -#define PFUZE100_SW3BSTANDBY_STBY_VAL 0x0 -#define PFUZE100_SW3BSTANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SW4STANDBY 75 -#define PFUZE100_SW4STANDBY_STBY_VAL 0 -#define PFUZE100_SW4STANDBY_STBY_M (0x3f<<0) -#define PFUZE100_SWBSTCON1 102 -#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2) -#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2) +#define PFUZE100_DEVICEID (0x0) +#define PFUZE100_REVID (0x3) +#define PFUZE100_SW1AMODE (0x23) #define PFUZE100_SW1ACON 36 #define PFUZE100_SW1ACON_SPEED_VAL (0x1<<6) /*default */ #define PFUZE100_SW1ACON_SPEED_M (0x3<<6) @@ -161,7 +139,13 @@ static struct regulator_init_data sw1a_init = { .valid_modes_mask = 0, .boot_on = 1, .always_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, #ifdef CONFIG_MX6_INTER_LDO_BYPASS .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), .consumer_supplies = sw1_consumers, @@ -189,7 +173,13 @@ static struct regulator_init_data sw1c_init = { .valid_modes_mask = 0, .always_on = 1, .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 975000,/*0.9V+6%*/ + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, }, + }, #ifdef CONFIG_MX6_INTER_LDO_BYPASS .num_consumer_supplies = ARRAY_SIZE(sw1c_consumers), .consumer_supplies = sw1c_consumers, @@ -397,17 +387,52 @@ static struct regulator_init_data vgen6_init = { static int pfuze100_init(struct mc_pfuze *pfuze) { - int ret; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY, - PFUZE100_SW1ASTANDBY_STBY_M, - PFUZE100_SW1ASTANDBY_STBY_VAL); + int ret, i; + unsigned int reg; + unsigned char value; + /*read Device ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value); if (ret) goto err; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, - PFUZE100_SW1CSTANDBY_STBY_M, - PFUZE100_SW1CSTANDBY_STBY_VAL); + if (value != 0x10) { + printk(KERN_ERR "wrong device id:%x!\n", value); + goto err; + } + + /*read Revision ID*/ + ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value); if (ret) goto err; + if (value == 0x10) { + printk(KERN_WARNING "PF100 1.0 chip found!\n"); + /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode + * except SW1C(APS) in normal and PFM mode in standby. + */ + for (i = 0; i < 7; i++) { + if (i == 2)/*SW1C*/ + value = 0xc;/*normal:APS mode;standby:PFM mode*/ + else + value = 0xd;/*normal:PWM mode;standby:PFM mode*/ + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } else { + /*set all switches APS in normal and PFM mode in standby*/ + for (i = 0; i < 7; i++) { + value = 0xc; + ret = pfuze_reg_write(pfuze, + PFUZE100_SW1AMODE + (i * 7), + value); + if (ret) + goto err; + } + + } + /*set SW1AB/SW1CDVSPEED as 25mV step each 4us,quick than 16us before.*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON, PFUZE100_SW1ACON_SPEED_M, diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S index dc4107dff7e8..4ec97e424237 100644 --- a/arch/arm/mach-mx6/mx6sl_wfi.S +++ b/arch/arm/mach-mx6/mx6sl_wfi.S @@ -29,12 +29,6 @@ ldr r7, [r1, #0x318] /* DRAM_DQM3 */ stmfd r9!, {r4-r7} - ldr r4, [r1, #0x344] /* DRAM_SDQS0 */ - ldr r5, [r1, #0x348] /* DRAM_SDQS1 */ - ldr r6, [r1, #0x34c] /* DRAM_SDQS2 */ - ldr r7, [r1, #0x350] /* DRAM_SDQS3 */ - stmfd r9!, {r4-r7} - ldr r4, [r1, #0x5c4] /* GPR_B0DS */ ldr r5, [r1, #0x5cc] /* GPR_B1DS */ ldr r6, [r1, #0x5d4] /* GPR_B2DS */ @@ -56,13 +50,16 @@ ldr r4, [r1, #0x330] /* DRAM_SDCKE0 */ ldr r5, [r1, #0x334] /* DRAM_SDCKE1 */ ldr r6, [r1, #0x320] /* DRAM_RESET */ - ldr r7, [r1, #0x5c8] /* GPR_CTLDS */ - stmfd r9!, {r4-r7} + stmfd r9!, {r4-r6} .endm .macro sl_ddr_io_restore + /* r9 points to IRAM stack. + * r1 points to IOMUX base address. + * r8 points to MMDC base address. + */ ldmea r9!, {r4-r7} str r4, [r1, #0x30c] /* DRAM_DQM0 */ str r5, [r1, #0x310] /* DRAM_DQM1 */ @@ -70,12 +67,6 @@ str r7, [r1, #0x318] /* DRAM_DQM3 */ ldmea r9!, {r4-r7} - str r4, [r1, #0x344] /* DRAM_SDQS0 */ - str r5, [r1, #0x348] /* DRAM_SDQS1 */ - str r6, [r1, #0x34c] /* DRAM_SDQS2 */ - str r7, [r1, #0x350] /* DRAM_SDQS3 */ - - ldmea r9!, {r4-r7} str r4, [r1, #0x5c4] /* GPR_B0DS */ str r5, [r1, #0x5cc] /* GPR_B1DS */ str r6, [r1, #0x5d4] /* GPR_B2DS */ @@ -93,11 +84,35 @@ str r6, [r1, #0x33c] /* DRAM_SODT0*/ str r7, [r1, #0x340] /* DRAM_SODT1*/ - ldmea r9!, {r4-r7} + ldmea r9!, {r4-r6} str r4, [r1, #0x330] /* DRAM_SDCKE0 */ str r5, [r1, #0x334] /* DRAM_SDCKE1 */ str r6, [r1, #0x320] /* DRAM_RESET */ - str r7, [r1, #0x5c8] /* GPR_CTLDS */ + + /* Need to reset the FIFO to avoid MMDC lockup + * caused because of floating/changing the + * configuration of many DDR IO pads. + */ + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =0x83c + ldr r6, [r8, r7] + orr r6, r6, #0x80000000 + str r6, [r8, r7] +fifo_reset1_wait: + ldr r6, [r8, r7] + and r6, r6, #0x80000000 + cmp r6, #0 + bne fifo_reset1_wait + + /* reset FIFO a second time */ + ldr r6, [r8, r7] + orr r6, r6, #0x80000000 + str r6, [r8, r7] +fifo_reset2_wait: + ldr r6, [r8, r7] + and r6, r6, #0x80000000 + cmp r6, #0 + bne fifo_reset2_wait .endm @@ -109,18 +124,6 @@ str r4, [r1, #0x314] /* DRAM_DQM2 */ str r4, [r1, #0x318] /* DRAM_DQM3 */ - /* Make sure the Pull Ups are enabled. - * So only reduce the drive stength, but - * leave the pull-ups in the original state. - * This is required for LPDDR2. - */ - ldr r4, [r1, #0x344] - orr r4, r4, #0x3000 - str r4, [r1, #0x344] /* DRAM_SDQS0 */ - str r4, [r1, #0x348] /* DRAM_SDQS1 */ - str r4, [r1, #0x34c] /* DRAM_SDQS2 */ - str r4, [r1, #0x350] /* DRAM_SDQS3 */ - str r4, [r1, #0x5c4] /* GPR_B0DS */ str r4, [r1, #0x5cc] /* GPR_B1DS */ str r4, [r1, #0x5d4] /* GPR_B2DS */ diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c index 2308e332dc44..a2a2798f93a0 100644 --- a/arch/arm/mach-mx6/pm.c +++ b/arch/arm/mach-mx6/pm.c @@ -68,12 +68,13 @@ #define LOCAL_TWD_INT_OFFSET 0xc #define ANATOP_REG_2P5_OFFSET 0x130 #define ANATOP_REG_CORE_OFFSET 0x140 +#define VDD3P0_VOLTAGE 3200000 static struct clk *cpu_clk; static struct clk *axi_clk; static struct clk *periph_clk; -static struct clk *axi_org_parent; static struct clk *pll3_usb_otg_main_clk; +static struct regulator *vdd3p0_regulator; static struct pm_platform_data *pm_data; @@ -179,6 +180,8 @@ static void usb_power_up_handler(void) static void disp_power_down(void) { +#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \ + !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE) if (cpu_is_mx6sl()) { __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET); __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET); @@ -195,10 +198,13 @@ static void disp_power_down(void) ~MXC_CCM_CCGRx_CG1_MASK, MXC_CCM_CCGR3); } +#endif } static void disp_power_up(void) { +#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \ + !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE) if (cpu_is_mx6sl()) { /* * Need to enable EPDC/LCDIF pix clock, and @@ -215,6 +221,7 @@ static void disp_power_up(void) __raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET); __raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET); } +#endif } static void mx6_suspend_store(void) @@ -336,8 +343,6 @@ static int mx6_suspend_enter(suspend_state_t state) } if (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY) { - if (pm_data && pm_data->suspend_enter) - pm_data->suspend_enter(); local_flush_tlb_all(); flush_cache_all(); @@ -348,9 +353,39 @@ static int mx6_suspend_enter(suspend_state_t state) save_gic_cpu_state(0, &gcs); } + if (pm_data && pm_data->suspend_enter) + pm_data->suspend_enter(); + suspend_in_iram(state, (unsigned long)iram_paddr, (unsigned long)suspend_iram_base, cpu_type); + if (pm_data && pm_data->suspend_exit) + pm_data->suspend_exit(); + + /* Reset the RBC counter. */ + /* All interrupts should be masked before the + * RBC counter is reset. + */ + /* Mask all interrupts. These will be unmasked by + * the mx6_suspend_restore routine below. + */ + __raw_writel(0xffffffff, gpc_base + 0x08); + __raw_writel(0xffffffff, gpc_base + 0x0c); + __raw_writel(0xffffffff, gpc_base + 0x10); + __raw_writel(0xffffffff, gpc_base + 0x14); + + /* Clear the RBC counter and RBC_EN bit. */ + /* Disable the REG_BYPASS_COUNTER. */ + __raw_writel(__raw_readl(MXC_CCM_CCR) & + ~MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR); + /* Make sure we clear REG_BYPASS_COUNT*/ + __raw_writel(__raw_readl(MXC_CCM_CCR) & + (~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR); + /* Need to wait for a minimum of 2 CLKILS (32KHz) for the + * counter to clear and reset. + */ + udelay(80); + if (arm_pg) { /* restore gic registers */ restore_gic_dist_state(0, &gds); @@ -366,8 +401,6 @@ static int mx6_suspend_enter(suspend_state_t state) __raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base + HW_ANADIG_ANA_MISC0_CLR); - if (pm_data && pm_data->suspend_exit) - pm_data->suspend_exit(); } else { cpu_do_idle(); } @@ -381,7 +414,12 @@ static int mx6_suspend_enter(suspend_state_t state) */ static int mx6_suspend_prepare(void) { - + int ret; + ret = regulator_disable(vdd3p0_regulator); + if (ret) { + printk(KERN_ERR "%s: failed to disable 3p0 regulator Err: %d\n", + __func__, ret); + } return 0; } @@ -390,6 +428,12 @@ static int mx6_suspend_prepare(void) */ static void mx6_suspend_finish(void) { + int ret; + ret = regulator_enable(vdd3p0_regulator); + if (ret) { + printk(KERN_ERR "%s: failed to enable 3p0 regulator Err: %d\n", + __func__, ret); + } } #ifdef CONFIG_MX6_INTER_LDO_BYPASS @@ -443,6 +487,7 @@ static struct platform_driver mx6_pm_driver = { static int __init pm_init(void) { + int ret = 0; scu_base = IO_ADDRESS(SCU_BASE_ADDR); gpc_base = IO_ADDRESS(GPC_BASE_ADDR); src_base = IO_ADDRESS(SRC_BASE_ADDR); @@ -500,6 +545,24 @@ static int __init pm_init(void) return PTR_ERR(pll3_usb_otg_main_clk); } + vdd3p0_regulator = regulator_get(NULL, "cpu_vdd3p0"); + if (IS_ERR(vdd3p0_regulator)) { + printk(KERN_ERR "%s: failed to get 3p0 regulator Err: %d\n", + __func__, ret); + return PTR_ERR(vdd3p0_regulator); + } + ret = regulator_set_voltage(vdd3p0_regulator, VDD3P0_VOLTAGE, + VDD3P0_VOLTAGE); + if (ret) { + printk(KERN_ERR "%s: failed to set 3p0 regulator voltage Err: %d\n", + __func__, ret); + } + ret = regulator_enable(vdd3p0_regulator); + if (ret) { + printk(KERN_ERR "%s: failed to enable 3p0 regulator Err: %d\n", + __func__, ret); + } + printk(KERN_INFO "PM driver module loaded\n"); return 0; @@ -509,6 +572,7 @@ static void __exit pm_cleanup(void) { /* Unregister the device structure */ platform_driver_unregister(&mx6_pm_driver); + regulator_put(vdd3p0_regulator); } module_init(pm_init); diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 0e4b534de6eb..6d24f22d156c 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -86,7 +86,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) int stop_mode = 0; void __iomem *anatop_base = IO_ADDRESS(ANATOP_BASE_ADDR); - u32 ccm_clpcr, anatop_val, reg; + u32 ccm_clpcr, anatop_val; ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); @@ -153,8 +153,15 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if (stop_mode > 0) { gpc_set_wakeup(gpc_wake_irq); /* Power down and power up sequence */ - __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); - __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); + /* The PUPSCR counter counts in terms of CLKIL (32KHz) cycles. + * The PUPSCR should include the time it takes for the ARM LDO to + * ramp up. + */ + __raw_writel(0xf0f, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); + /* The PDNSCR is a counter that counts in IPG_CLK cycles. This counter + * can be set to minimum values to power down faster. + */ + __raw_writel(0x101, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); if (stop_mode >= 2) { /* dormant mode, need to power off the arm core */ __raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET); @@ -198,25 +205,17 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) HW_ANADIG_REG_2P5); } } - /* DL's TO1.0 can't support DSM mode due to ipg glitch */ - if ((mx6dl_revision() != IMX_CHIP_REVISION_1_0) - && stop_mode != 3) - __raw_writel(__raw_readl(MXC_CCM_CCR) | - MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR); - if (stop_mode != 3) { /* Make sure we clear WB_COUNT * and re-config it. */ __raw_writel(__raw_readl(MXC_CCM_CCR) & - (~MXC_CCM_CCR_WB_COUNT_MASK) & - (~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR); - udelay(80); - /* Reconfigurate WB and RBC counter, need to set WB counter + (~MXC_CCM_CCR_WB_COUNT_MASK), + MXC_CCM_CCR); + /* Reconfigure WB, need to set WB counter * to 0x7 to make sure it work normally */ __raw_writel(__raw_readl(MXC_CCM_CCR) | - (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET) | - (0x20 << MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET), + (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET), MXC_CCM_CCR); /* Set WB_PER enable */ diff --git a/arch/arm/plat-mxc/devices/platform-imx-caam.c b/arch/arm/plat-mxc/devices/platform-imx-caam.c index 316249032a8d..aaaf501f179c 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-caam.c +++ b/arch/arm/plat-mxc/devices/platform-imx-caam.c @@ -31,6 +31,8 @@ const struct imx_caam_data imx6q_imx_caam_data __initconst = { .iobase_caam = MXC_CAAM_BASE_ADDR, + .iobase_caam_sm = CAAM_SECMEM_BASE_ADDR, + .iobase_snvs = MX6Q_SNVS_BASE_ADDR, .irq_sec_vio = MXC_INT_SNVS_SEC, .irq_snvs = MX6Q_INT_SNVS, .jr[0].offset_jr = 0x1000, @@ -51,6 +53,18 @@ struct platform_device *__init imx_add_caam( .end = data->iobase_caam + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { + /* Define range for secure memory */ + .name = "iobase_caam_sm", + .start = data->iobase_caam_sm, + .end = data->iobase_caam_sm + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + /* Define range for SNVS */ + .name = "iobase_snvs", + .start = data->iobase_snvs, + .end = data->iobase_snvs + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { /* Define interrupt for security violations */ .name = "irq_sec_vio", .start = data->irq_sec_vio, diff --git a/arch/arm/plat-mxc/devices/platform-imx-pm.c b/arch/arm/plat-mxc/devices/platform-imx-pm.c index f901e18368c2..5b865ad48932 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-pm.c +++ b/arch/arm/plat-mxc/devices/platform-imx-pm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -30,6 +30,11 @@ const struct imx_pm_imx_data imx6q_pm_imx_data[] __initconst = imx_pm_imx_data_entry_single(MX6Q); #endif +#ifdef CONFIG_SOC_IMX6SL +const struct imx_pm_imx_data imx6sl_pm_imx_data[] __initconst = + imx_pm_imx_data_entry_single(MX6SL); +#endif + struct platform_device *__init imx_add_pm_imx( const struct imx_pm_imx_data *data, const struct pm_platform_data *pdata) diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c index 0829ff8999ae..4aaaecc25641 100755 --- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -115,6 +115,6 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx( }, }; - return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); + return imx_add_platform_device_dmamask("sdhci-esdhc-imx", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c index 32a6c06511a4..bdf91df941f5 100755 --- a/arch/arm/plat-mxc/dvfs_core.c +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -115,7 +115,9 @@ static struct delayed_work dvfs_core_handler; */ static struct clk *pll1_sw_clk; static struct clk *cpu_clk; +#ifdef CONFIG_ARCH_MX5 static struct clk *gpu_clk; +#endif static struct clk *dvfs_clk; static int cpu_op_nr; @@ -761,9 +763,9 @@ void stop_dvfs(void) u32 reg = 0; unsigned long flags; u32 curr_cpu; - u32 old_loops_per_jiffy; -#ifdef CONFIG_CPU_FREQ int cpu; +#ifndef CONFIG_SMP + u32 old_loops_per_jiffy; #endif if (dvfs_core_is_active) { diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index e004901bb63b..cc6f7781c31c 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -112,9 +112,11 @@ struct imx_caam_jr_data { }; struct imx_caam_data { - resource_size_t iobase_caam; - resource_size_t irq_sec_vio; - resource_size_t irq_snvs; + resource_size_t iobase_caam; /* entirety of CAAM register map */ + resource_size_t iobase_caam_sm; /* base of secure memory */ + resource_size_t iobase_snvs; /* base of SNVS */ + resource_size_t irq_sec_vio; /* SNVS security violation */ + resource_size_t irq_snvs; /* SNVS consolidated (incl. RTC) */ struct imx_caam_jr_data jr[4]; /* offset+IRQ for each possible ring */ }; diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h index 3fccb3be9e15..af2edb84a0f2 100644 --- a/arch/arm/plat-mxc/include/mach/dma.h +++ b/arch/arm/plat-mxc/include/mach/dma.h @@ -101,5 +101,6 @@ static inline int mxs_dma_is_apbx(struct dma_chan *chan) return !strcmp(dev_name(chan->device->dev), "mxs-dma-apbx"); } +void sdma_set_event_pending(struct dma_chan *chan); #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h index 9226af18f7ee..fe107cffca7b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h @@ -566,7 +566,7 @@ #define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \ IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D30__UART3_CTS \ - IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0) + IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D30__GPIO_3_30 \ IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0) #define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index c53028f984d1..8bdfe79785df 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -161,14 +161,16 @@ typedef u64 iomux_v3_cfg_t; #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* - * setups a single pad in the iomuxer + * read/write a single pad in the iomuxer */ +int mxc_iomux_v3_get_pad(iomux_v3_cfg_t *pad); int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); /* - * setups mutliple pads + * read/write mutliple pads * convenient way to call the above function with tables */ + int mxc_iomux_v3_get_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); /* diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index dfb3f6489cc1..48b04b104560 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -83,8 +83,8 @@ #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00103FFF +#define CAAM_SECMEM_BASE_ADDR 0x00100000 +#define CAAM_SECMEM_END_ADDR 0x00103FFF #define APBH_DMA_ARB_BASE_ADDR 0x00110000 #define APBH_DMA_ARB_END_ADDR 0x00117FFF #define MX6Q_HDMI_ARB_BASE_ADDR 0x00120000 diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h index 0c0fa2aad38b..7a6e24f2b0dd 100755 --- a/arch/arm/plat-mxc/include/mach/mxc_vpu.h +++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h @@ -67,6 +67,7 @@ struct vpu_mem_desc { #define BIT_INT_REASON 0x174 #define MJPEG_PIC_STATUS_REG 0x3004 +#define MBC_SET_SUBBLK_EN 0x4A0 #define BIT_WORK_CTRL_BUF_BASE 0x100 #define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) @@ -77,7 +78,11 @@ struct vpu_mem_desc { #define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) #define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) +#ifndef CONFIG_ARCH_MX6 #define BIT_RESET_CTRL 0x11C +#else +#define BIT_RESET_CTRL 0x128 +#endif /* i could be 0, 1, 2, 3 */ #define BIT_RD_PTR_BASE 0x120 diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 85b7e176981b..b88208c10de9 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -56,6 +56,36 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); +/* + * Read a single pad in the iomuxer + */ +int mxc_iomux_v3_get_pad(iomux_v3_cfg_t *pad) +{ + u32 mux_ctrl_ofs = (*pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 pad_ctrl_ofs = (*pad & MUX_PAD_CTRL_OFS_MASK) + >> MUX_PAD_CTRL_OFS_SHIFT; + u32 sel_input_ofs = (*pad & MUX_SEL_INPUT_OFS_MASK) + >> MUX_SEL_INPUT_OFS_SHIFT; + u32 mux_mode = 0; + u32 sel_input = 0; + u32 pad_ctrl = 0; + iomux_v3_cfg_t pad_info = 0; + + mux_mode = __raw_readl(base + mux_ctrl_ofs) & 0xFF; + pad_ctrl = __raw_readl(base + pad_ctrl_ofs) & 0x1FFFF; + sel_input = __raw_readl(base + sel_input_ofs) & 0x7; + + pad_info = (((iomux_v3_cfg_t)mux_mode << MUX_MODE_SHIFT) | \ + ((iomux_v3_cfg_t)pad_ctrl << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_v3_cfg_t)sel_input << MUX_SEL_INPUT_SHIFT)); + + *pad &= ~(MUX_MODE_MASK | MUX_PAD_CTRL_MASK | MUX_SEL_INPUT_MASK); + *pad |= pad_info; + + return 0; +} + + int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) { iomux_v3_cfg_t *p = pad_list; @@ -72,6 +102,22 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) } EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); +/* + * Read multiple pads in the iomuxer + */ +int mxc_iomux_v3_get_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) +{ + iomux_v3_cfg_t *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + mxc_iomux_v3_get_pad(p); + p++; + } + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_get_multiple_pads); + void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value) { int i = 0; |