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authorStefan Agner <stefan@agner.ch>2014-08-19 00:32:47 +0200
committerStefan Agner <stefan@agner.ch>2016-02-10 18:42:30 -0800
commit61ead435105de722854e090c724dd2b7348b914e (patch)
tree04dfaa84a9a6fbefc5cc61cbbb6115af9e5db8e0 /arch
parent576ffa9d2fc668251444cf247f0fad6efdfd76f7 (diff)
ARM: dts: vf610: add on-chip SRAM
Add Vybrids massive on-chip SRAM areas. Make use of the memory region functionality to denominate the retained SRAM area in LPSTOP2 and LPSTOP3.
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 3d9da56d0a5d..dc2984288f27 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -57,6 +57,43 @@
interrupt-parent = <&gpc>;
ranges;
+ ocram0: sram@3f000000 {
+ compatible = "mmio-sram";
+ reg = <0x3f000000 0x40000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x3f000000 0x40000>;
+
+ stbyram1@0 {
+ reg = <0x0 0x4000>;
+ label = "stbyram1";
+ pool;
+ };
+
+ stbyram2@4000 {
+ reg = <0x4000 0xc000>;
+ label = "stbyram2";
+ pool;
+ };
+ };
+
+ ocram1: sram@3f040000 {
+ compatible = "mmio-sram";
+ reg = <0x3f040000 0x40000>;
+ };
+
+ gfxram0: sram@3f400000 {
+ compatible = "mmio-sram";
+ reg = <0x3f400000 0x80000>;
+ };
+
+ /* used by L2 cache */
+ gfxram1: sram@3f480000 {
+ compatible = "mmio-sram";
+ reg = <0x3f480000 0x80000>;
+ };
+
aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;