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authorRichard Zhu <r65037@freescale.com>2010-07-12 15:29:24 +0800
committerRichard Zhu <r65037@freescale.com>2010-07-13 10:46:45 +0800
commitd4ff4e8c9d07cf00311eef2627e573fddd46b7be (patch)
tree668540c3da634d97a2b938dd62e1c2b0e513cc4c /arch
parent57ed2d4e12150348f0672afde2823ec45fe26d80 (diff)
ENGR00124255 Reconfigure MX5x's eSDHC iomux PAD's configurations
Reconfigure the PAD's configurations to level up the HW timing compatibility. MX51:Some MMC cards such as transcend mmc plus cards can't be recognized and initialized correctly on the second esdhc slot of the BBG boards that populated the new DDR chips. MX53:Same Kingstone SDHC card can work well on EVK REVA board, but failed in initialization on EVK REVB board without any sw modifications. After adjust the slot pin's pad configurations, fix the HW compatible issues listed above. Signed-off-by: Richard Zhu <r65037@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx5/mx51_babbage_gpio.c56
-rw-r--r--arch/arm/mach-mx5/mx53_evk_gpio.c64
2 files changed, 88 insertions, 32 deletions
diff --git a/arch/arm/mach-mx5/mx51_babbage_gpio.c b/arch/arm/mach-mx5/mx51_babbage_gpio.c
index 5dfc7fedec2c..aace94dbfdd3 100644
--- a/arch/arm/mach-mx5/mx51_babbage_gpio.c
+++ b/arch/arm/mach-mx5/mx51_babbage_gpio.c
@@ -270,27 +270,39 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
},
{
MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
@@ -302,27 +314,39 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
},
{
MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
- MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
- MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
- MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
- MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+ MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX51_PIN_GPIO1_4, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c
index 994fbdb78b71..76094607fecd 100644
--- a/arch/arm/mach-mx5/mx53_evk_gpio.c
+++ b/arch/arm/mach-mx5/mx53_evk_gpio.c
@@ -515,68 +515,100 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
/* esdhc1 */
{
MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
/* esdhc3 */
{
MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{
MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2,
- (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
+ (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
+ | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
+ | PAD_CTL_SRE_FAST),
},
{ /* FEC pins */
MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0,
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-15 10:56:40 +0000