diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-10-12 05:40:03 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-10-15 02:57:52 -0500 |
| commit | 2a2f65bd07ad0f947794c2e5f2f825121805d663 (patch) | |
| tree | df606c7d2655405ca50c88e88b5dacd26b366342 /arch | |
| parent | 6337b9566e2370efc95b979b1b3716e88b821a35 (diff) | |
ENGR00229441 MX6SL-Reset MMDC read FIFO in low power IDLE
MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/mx6sl_wfi.S | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S index dc4107dff7e8..e8936b6862c8 100644 --- a/arch/arm/mach-mx6/mx6sl_wfi.S +++ b/arch/arm/mach-mx6/mx6sl_wfi.S @@ -99,6 +99,31 @@ str r6, [r1, #0x320] /* DRAM_RESET */ str r7, [r1, #0x5c8] /* GPR_CTLDS */ + /* Need to reset the FIFO to avoid MMDC lockup + * caused because of floating/changing the + * configuration of many DDR IO pads. + */ + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =0x83c + ldr r6, [r1, r7] + orr r6, r6, #0x80000000 + str r6, [r1, r7] +fifo_reset1_wait: + ldr r6, [r1, r7] + and r6, r6, #0x80000000 + cmp r6, #0 + bne fifo_reset1_wait + + /* reset FIFO a second time */ + ldr r6, [r1, r7] + orr r6, r6, #0x80000000 + str r6, [r1, r7] +fifo_reset2_wait: + ldr r6, [r1, r7] + and r6, r6, #0x80000000 + cmp r6, #0 + bne fifo_reset2_wait + .endm .macro sl_ddr_io_set_lpm |