diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2015-01-22 16:48:26 +0100 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2015-08-05 17:29:25 +0200 |
| commit | 93d5225ec25c4b96309690b42c47be58c6ff5b85 (patch) | |
| tree | 503f189a5d3192a9a44a87e3d498f33a46309913 /arch | |
| parent | f9d70155304bc2a4207418dba6821a64a0a63e37 (diff) | |
ARM: imx: clk-vf610: do not set specific divisor for DCU
Do not specify the DCU clock to avoid the main input clock being
divided. This maximizes the input clock for the DCU subsystem to
about 452MHz. The DCU internal clock divider allows to divide by
up to 255, which allows small enougth pixel clocks for most cases.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-vf610.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index ad11bd62d2da..843e8fd68822 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -404,7 +404,6 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); clk_set_parent(clk[VF610_CLK_DCU0_SEL], clk[VF610_CLK_PLL1_PFD2]); - clk_set_rate(clk[VF610_CLK_DCU0_DIV], 113200000); for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clk[clks_init_on[i]]); |