Merge commit 'rel_imx_3.0.35_12.10.02_RC2' into imx_3.0.35_android_r13.5-ga

Conflicts:
	arch/arm/mach-mx6/pm.c

Signed-off-by: Jack Lee <jack.lee@freescale.com>

13 files changed, 217 insertions, 136 deletions

diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig
index ac7afdfdf5ff..41f43e5c0d63 100644
--- a/arch/arm/configs/imx6s_defconfig
+++ b/arch/arm/configs/imx6s_defconfig
@@ -1620,7 +1620,7 @@ CONFIG_MXC_CAMERA_OV5640=y
 # CONFIG_MXC_CAMERA_OV5640_MIPI is not set
 CONFIG_MXC_CAMERA_SENSOR_CLK=y
 CONFIG_VIDEO_MXC_OUTPUT=y
-# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
+CONFIG_VIDEO_MXC_PXP_V4L2=y
 # CONFIG_VIDEO_MXC_OPL is not set
 # CONFIG_VIDEO_CPIA2 is not set
 # CONFIG_VIDEO_TIMBERDALE is not set
diff --git a/arch/arm/mach-mx6/board-mx6sl_common.h b/arch/arm/mach-mx6/board-mx6sl_common.h
index 465863ec504d..1db30542391f 100644
--- a/arch/arm/mach-mx6/board-mx6sl_common.h
+++ b/arch/arm/mach-mx6/board-mx6sl_common.h
@@ -389,40 +389,11 @@ static iomux_v3_cfg_t mx6sl_brd_spdc_disable_pads[] = {
 	MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14,
 };
 
-static iomux_v3_cfg_t mx6sl_brd_csi_enable_pads[] = {
-	MX6SL_PAD_EPDC_GDRL__CSI_MCLK,
-	MX6SL_PAD_EPDC_SDCE3__I2C3_SDA,
-	MX6SL_PAD_EPDC_SDCE2__I2C3_SCL,
-	MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK,
-	MX6SL_PAD_EPDC_GDSP__CSI_VSYNC,
-	MX6SL_PAD_EPDC_GDOE__CSI_HSYNC,
-	MX6SL_PAD_EPDC_SDLE__CSI_D_9,
-	MX6SL_PAD_EPDC_SDCLK__CSI_D_8,
-	MX6SL_PAD_EPDC_D7__CSI_D_7,
-	MX6SL_PAD_EPDC_D6__CSI_D_6,
-	MX6SL_PAD_EPDC_D5__CSI_D_5,
-	MX6SL_PAD_EPDC_D4__CSI_D_4,
-	MX6SL_PAD_EPDC_D3__CSI_D_3,
-	MX6SL_PAD_EPDC_D2__CSI_D_2,
-	MX6SL_PAD_EPDC_D1__CSI_D_1,
-	MX6SL_PAD_EPDC_D0__CSI_D_0,
-
-	MX6SL_PAD_EPDC_SDSHR__GPIO_1_26,	/* CMOS_RESET_B GPIO */
-	MX6SL_PAD_EPDC_SDOE__GPIO_1_25,		/* CMOS_PWDN GPIO */
-};
-
 static iomux_v3_cfg_t mx6sl_brd_elan_pads[] = {
 	MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10,	/* INT */
 	MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9,	/* CE */
 	MX6SL_PAD_KEY_COL6__GPIO_4_4,		/* RST */
 };
-	/* uart2 pins */
-static iomux_v3_cfg_t mx6sl_uart2_pads[] = {
-	MX6SL_PAD_SD2_DAT5__UART2_TXD,
-	MX6SL_PAD_SD2_DAT4__UART2_RXD,
-	MX6SL_PAD_SD2_DAT6__UART2_RTS,
-	MX6SL_PAD_SD2_DAT7__UART2_CTS,
-};
 
 #define MX6SL_USDHC_8BIT_PAD_SETTING(id, speed)	\
 mx6sl_sd##id##_##speed##mhz[] = {		\
diff --git a/arch/arm/mach-mx6/board-mx6sl_evk.c b/arch/arm/mach-mx6/board-mx6sl_evk.c
index 03705bb105ae..6b479a2a9500 100644
--- a/arch/arm/mach-mx6/board-mx6sl_evk.c
+++ b/arch/arm/mach-mx6/board-mx6sl_evk.c
@@ -86,6 +86,36 @@ extern int __init mx6sl_evk_init_pfuze100(u32 int_gpio);
 
 static int csi_enabled;
 
+static iomux_v3_cfg_t mx6sl_brd_csi_enable_pads[] = {
+	MX6SL_PAD_EPDC_GDRL__CSI_MCLK,
+	MX6SL_PAD_EPDC_SDCE3__I2C3_SDA,
+	MX6SL_PAD_EPDC_SDCE2__I2C3_SCL,
+	MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK,
+	MX6SL_PAD_EPDC_GDSP__CSI_VSYNC,
+	MX6SL_PAD_EPDC_GDOE__CSI_HSYNC,
+	MX6SL_PAD_EPDC_SDLE__CSI_D_9,
+	MX6SL_PAD_EPDC_SDCLK__CSI_D_8,
+	MX6SL_PAD_EPDC_D7__CSI_D_7,
+	MX6SL_PAD_EPDC_D6__CSI_D_6,
+	MX6SL_PAD_EPDC_D5__CSI_D_5,
+	MX6SL_PAD_EPDC_D4__CSI_D_4,
+	MX6SL_PAD_EPDC_D3__CSI_D_3,
+	MX6SL_PAD_EPDC_D2__CSI_D_2,
+	MX6SL_PAD_EPDC_D1__CSI_D_1,
+	MX6SL_PAD_EPDC_D0__CSI_D_0,
+
+	MX6SL_PAD_EPDC_SDSHR__GPIO_1_26,	/* CMOS_RESET_B GPIO */
+	MX6SL_PAD_EPDC_SDOE__GPIO_1_25,		/* CMOS_PWDN GPIO */
+};
+
+/* uart2 pins */
+static iomux_v3_cfg_t mx6sl_uart2_pads[] = {
+	MX6SL_PAD_SD2_DAT5__UART2_TXD,
+	MX6SL_PAD_SD2_DAT4__UART2_RXD,
+	MX6SL_PAD_SD2_DAT6__UART2_RTS,
+	MX6SL_PAD_SD2_DAT7__UART2_CTS,
+};
+
 enum sd_pad_mode {
 	SD_PAD_MODE_LOW_SPEED,
 	SD_PAD_MODE_MED_SPEED,
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index 9d18423c85c5..f25882bd40d1 100644
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -110,7 +110,7 @@ static struct clk *pll1;
 static struct clk *pll1_sw_clk;
 static struct clk *pll3_sw_clk;
 static struct clk *pll2_200;
-static struct clk *mmdc_ch0_axi;
+struct clk *mmdc_ch0_axi;
 static struct clk *pll3_540;
 
 static struct delayed_work low_bus_freq_handler;
@@ -155,8 +155,6 @@ void reduce_bus_freq(void)
 		u32  div;
 		unsigned long flags;
 
-		spin_lock_irqsave(&freq_lock, flags);
-
 		if (high_bus_freq_mode) {
 			/* Set periph_clk to be sourced from OSC_CLK */
 			/* Set AXI to 24MHz. */
@@ -170,8 +168,11 @@ void reduce_bus_freq(void)
 		if (lp_audio_freq) {
 			/* PLL2 is on in this mode, as DDR is at 50MHz. */
 			/* Now change DDR freq while running from IRAM. */
+
+			spin_lock_irqsave(&freq_lock, flags);
 			mx6sl_ddr_freq_change_iram(DDR_AUDIO_CLK,
 							low_bus_freq_mode);
+			spin_unlock_irqrestore(&freq_lock, flags);
 
 			if (low_bus_freq_mode) {
 				/* Swtich ARM to run off PLL2_PFD2_400MHz
@@ -213,14 +214,15 @@ void reduce_bus_freq(void)
 				;
 			clk_set_parent(pll1_sw_clk, pll1);
 
+			spin_lock_irqsave(&freq_lock, flags);
 			/* Now change DDR freq while running from IRAM. */
 			mx6sl_ddr_freq_change_iram(LPAPM_CLK,
 					low_bus_freq_mode);
+			spin_unlock_irqrestore(&freq_lock, flags);
 
 			low_bus_freq_mode = 1;
 			audio_bus_freq_mode = 0;
 		}
-		spin_unlock_irqrestore(&freq_lock, flags);
 	}
 	high_bus_freq_mode = 0;
 
@@ -325,6 +327,7 @@ int set_high_bus_freq(int high_bus_freq)
 		spin_lock_irqsave(&freq_lock, flags);
 		/* Change DDR freq in IRAM. */
 		mx6sl_ddr_freq_change_iram(ddr_normal_rate, low_bus_freq_mode);
+		spin_unlock_irqrestore(&freq_lock, flags);
 
 		/* Set periph_clk to be sourced from pll2_pfd2_400M */
 		/* First need to set the divider before changing the */
@@ -348,7 +351,6 @@ int set_high_bus_freq(int high_bus_freq)
 		high_bus_freq_mode = 1;
 		low_bus_freq_mode = 0;
 		audio_bus_freq_mode = 0;
-		spin_unlock_irqrestore(&freq_lock, flags);
 	} else {
 		clk_enable(pll3);
 		if (high_bus_freq) {
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 19a98aa167c5..9ceff4f07c71 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -101,9 +101,7 @@ DEFINE_SPINLOCK(mx6sl_clk_lock);
 	u32 gpt_ticks; \
 	u32 gpt_cnt; \
 	u32 reg; \
-	unsigned long flags; \
 	int result = 1; \
-	spin_lock_irqsave(&mx6sl_clk_lock, flags); \
 	gpt_rate = clk_get_rate(&gpt_clk[0]); \
 	gpt_ticks = timeout / (1000000000 / gpt_rate); \
 	reg = __raw_readl(timer_base + V2_TSTAT);\
@@ -133,7 +131,6 @@ DEFINE_SPINLOCK(mx6sl_clk_lock);
 			} \
 		} \
 	} \
-	spin_unlock_irqrestore(&mx6sl_clk_lock, flags); \
 	result; \
 })
 
diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c
index 99336d873756..e6ef0261a285 100644
--- a/arch/arm/mach-mx6/cpu_op-mx6.c
+++ b/arch/arm/mach-mx6/cpu_op-mx6.c
@@ -217,32 +217,24 @@ static struct cpu_op mx6sl_cpu_op_1G[] = {
 	 .pll_rate = 996000000,
 	 .cpu_rate = 996000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1225000,
-	 .soc_voltage = 1225000,
-	 .cpu_voltage = 1275000,},
+	 .pu_voltage = 1200000,
+	 .soc_voltage = 1200000,
+	 .cpu_voltage = 1250000,},
 	{
 	 .pll_rate = 792000000,
 	 .cpu_rate = 792000000,
 	 .cpu_podf = 0,
 	 .pu_voltage = 1150000,
 	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1200000,},
+	 .cpu_voltage = 1150000,},
 	{
 	 .pll_rate = 396000000,
 	 .pll_lpm_rate = 792000000,
 	 .cpu_rate = 396000000,
 	 .cpu_podf = 0,
-	 .pu_voltage = 1050000,
-	 .soc_voltage = 1050000,
-	 .cpu_voltage = 1100000,},
-	 {
-	  .pll_rate = 396000000,
-	 .pll_lpm_rate = 792000000,
-	  .cpu_rate = 198000000,
-	  .cpu_podf = 1,
-	  .pu_voltage = 1050000,
-	  .soc_voltage = 1050000,
-	  .cpu_voltage = 1050000,},
+	 .pu_voltage = 1150000,
+	 .soc_voltage = 1150000,
+	 .cpu_voltage = 950000,},
 };
 
 static struct cpu_op mx6sl_cpu_op[] = {
@@ -252,23 +244,15 @@ static struct cpu_op mx6sl_cpu_op[] = {
 	 .cpu_podf = 0,
 	 .pu_voltage = 1150000,
 	 .soc_voltage = 1150000,
-	 .cpu_voltage = 1200000,},
+	 .cpu_voltage = 1150000,},
 	 {
 	  .pll_rate = 396000000,
 	 .pll_lpm_rate = 792000000,
 	  .cpu_rate = 396000000,
 	  .cpu_podf = 0,
-	 .pu_voltage = 1050000,
-	 .soc_voltage = 1050000,
-	 .cpu_voltage = 1100000,},
-	{
-	 .pll_rate = 396000000,
-	 .pll_lpm_rate = 792000000,
-	 .cpu_rate = 198000000,
-	 .cpu_podf = 1,
-	  .pu_voltage = 1050000,
-	  .soc_voltage = 1050000,
-	  .cpu_voltage = 1050000,},
+	 .pu_voltage = 1150000,
+	 .soc_voltage = 1150000,
+	 .cpu_voltage = 950000,},
 };
 
 static struct dvfs_op dvfs_core_setpoint_1_2G[] = {
diff --git a/arch/arm/mach-mx6/cpu_regulator-mx6.c b/arch/arm/mach-mx6/cpu_regulator-mx6.c
index 5019f8bedff2..8eb976d2eefd 100644
--- a/arch/arm/mach-mx6/cpu_regulator-mx6.c
+++ b/arch/arm/mach-mx6/cpu_regulator-mx6.c
@@ -62,7 +62,9 @@ void mx6_cpu_regulator_init(void)
 {
 	int cpu;
 	u32 curr_cpu = 0;
-
+#ifndef CONFIG_SMP
+	unsigned long old_loops_per_jiffy;
+#endif
 	external_pureg = 0;
 	cpu_regulator = regulator_get(NULL, gp_reg_id);
 	if (IS_ERR(cpu_regulator))
@@ -90,7 +92,7 @@ void mx6_cpu_regulator_init(void)
 					curr_cpu / 1000,
 					clk_get_rate(cpu_clk) / 1000);
 #else
-			u32 old_loops_per_jiffy = loops_per_jiffy;
+			old_loops_per_jiffy = loops_per_jiffy;
 
 			loops_per_jiffy =
 				mx6_cpu_jiffies(old_loops_per_jiffy,
diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S
index 1987581e56aa..f712700a8e68 100644
--- a/arch/arm/mach-mx6/mx6_suspend.S
+++ b/arch/arm/mach-mx6/mx6_suspend.S
@@ -233,6 +233,11 @@ wait_for_pll_lock:
 	bic	r6, r6, #0x2000000
 	str	r6, [r3, #0x14]
 
+periph_clk_switch1:
+	ldr	r6, [r3, #0x48]
+	cmp	r6, #0
+	bne     periph_clk_switch1
+
 	/* Set the dividers to default value. */
 	ldr	r6, [r3, #0x14]
 	bic	r6, r6, #0x70000
@@ -241,14 +246,9 @@ wait_for_pll_lock:
 	str	r6, [r3, #0x14]
 
 ahb_podf1:
-	ldr	r0, [r3, #0x48]
-	cmp	r0, #0
-	bne	ahb_podf1
-
-periph_clk_switch1:
 	ldr	r6, [r3, #0x48]
 	cmp	r6, #0
-	bne     periph_clk_switch1
+	bne	ahb_podf1
 
 	/* Move MMDC back to PLL2_PFD2_400 */
 	ldr	r6, [r3, #0x14]
@@ -262,7 +262,7 @@ mmdc_loop2:
 
 	/* Set DDR clock to divide by 1. */
 	ldr	r6, [r3, #0x14]
-	bic	r6, r0, #0x38
+	bic	r6, r6, #0x38
 	str	r6, [r3, #0x14]
 
 mmdc_div1:
@@ -1099,6 +1099,12 @@ set ddr iomux to low power mode
 	ldr	r1, =CCM_BASE_ADDR
 	add	r1, r1, #PERIPBASE_VIRT
 	ldr	r0, [r1]
+	ldr	r1, =GPC_BASE_ADDR
+	add	r1, r1, #PERIPBASE_VIRT
+	ldr	r0, [r1]
+	ldr	r1, =CCM_BASE_ADDR
+	add	r1, r1, #PERIPBASE_VIRT
+	ldr	r0, [r1]
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	ldr	r1, =ANATOP_BASE_ADDR
 	add	r1, r1, #PERIPBASE_VIRT
@@ -1173,6 +1179,66 @@ save resume pointer into SRC_GPR1
 	add	r1, r1, #PERIPBASE_VIRT
 	str	r3, [r1, #SRC_GPR1_OFFSET]
 
+	/* Mask all GPC interrupts before
+	  * enabling the RBC counters to
+	  * avoid the counter starting too
+	  * early if an interupt is already
+	  * pending.
+	  */
+	ldr	r3, =GPC_BASE_ADDR
+	add	r3, r3, #PERIPBASE_VIRT
+	ldr	r4, [r3, #0x08]
+	ldr	r5, [r3, #0x0c]
+	ldr	r6, [r3, #0x10]
+	ldr	r7, [r3, #0x14]
+
+	ldr	r8, =0xffffffff
+	str	r8, [r3, #0x08]
+	str	r8, [r3, #0x0c]
+	str	r8, [r3, #0x10]
+	str	r8, [r3, #0x14]
+
+	/* Enable the RBC bypass counter here
+	 * to hold off the interrupts.
+	 * RBC counter = 32 (1ms)
+	 * Minimum RBC delay should be
+	 * 400us for the analog LDOs to
+	 * power down.
+	 */
+	ldr	r1, =CCM_BASE_ADDR
+	add	r1, r1, #PERIPBASE_VIRT
+	ldr	r8, [r1, #0x0]
+	ldr	r0, =0x7E00000
+	bic	r8, r8, r0
+	ldr	r0, =0x4000000
+	orr	r8, r8, r0
+	str	r8, [r1, #0x0]
+
+	/* Enable the counter. */
+	ldr	r8, [r1, #0x0]
+	orr	r8, r8, #0x8000000
+	str	r8, [r1, #0x0]
+
+	/* Unmask all the GPC interrupts. */
+	str	r4, [r3, #0x08]
+	str	r5, [r3, #0x0c]
+	str	r6, [r3, #0x10]
+	str	r7, [r3, #0x14]
+
+	/* Now delay for a short while (3usec)
+	  * ARM is at 1GHz at this point
+	  * so a short loop should be enough.
+	  * This delay is required to ensure that
+	  * the RBC counter can start counting in case an
+	  * interrupt is already pending or in case an interrupt
+	  * arrives just as ARM is about to assert DSM_request.
+	  */
+	ldr	r4, =2000
+rbc_loop:
+	sub	r4, r4, #0x1
+	cmp	r4, #0x0
+	bne	rbc_loop
+
 #ifdef CONFIG_MX6_INTER_LDO_BYPASS
 	ldr	r1, =ANATOP_BASE_ADDR
 	add	r1, r1, #PERIPBASE_VIRT
diff --git a/arch/arm/mach-mx6/mx6sl_wfi.S b/arch/arm/mach-mx6/mx6sl_wfi.S
index dc4107dff7e8..4ec97e424237 100644
--- a/arch/arm/mach-mx6/mx6sl_wfi.S
+++ b/arch/arm/mach-mx6/mx6sl_wfi.S
@@ -29,12 +29,6 @@
 	ldr	r7, [r1, #0x318] /* DRAM_DQM3 */
 	stmfd	r9!, {r4-r7}
 
-	ldr	r4, [r1, #0x344] /* DRAM_SDQS0 */
-	ldr	r5, [r1, #0x348] /* DRAM_SDQS1 */
-	ldr	r6, [r1, #0x34c] /* DRAM_SDQS2 */
-	ldr	r7, [r1, #0x350] /* DRAM_SDQS3 */
-	stmfd	r9!, {r4-r7}
-
 	ldr	r4, [r1, #0x5c4] /* GPR_B0DS */
 	ldr	r5, [r1, #0x5cc] /* GPR_B1DS */
 	ldr	r6, [r1, #0x5d4] /* GPR_B2DS */
@@ -56,13 +50,16 @@
 	ldr	r4, [r1, #0x330] /* DRAM_SDCKE0 */
 	ldr	r5, [r1, #0x334] /* DRAM_SDCKE1 */
 	ldr	r6, [r1, #0x320] /* DRAM_RESET */
-	ldr	r7, [r1, #0x5c8] /* GPR_CTLDS */
-	stmfd	r9!, {r4-r7}
+	stmfd	r9!, {r4-r6}
 
 	.endm
 
 	.macro	sl_ddr_io_restore
 
+	/* r9 points to IRAM stack.
+	  * r1 points to IOMUX base address.
+	  * r8 points to MMDC  base address.
+	  */
 	ldmea	r9!, {r4-r7}
 	str	r4, [r1, #0x30c] /* DRAM_DQM0 */
 	str	r5, [r1, #0x310] /* DRAM_DQM1 */
@@ -70,12 +67,6 @@
 	str	r7, [r1, #0x318] /* DRAM_DQM3 */
 
 	ldmea	r9!, {r4-r7}
-	str	r4, [r1, #0x344] /* DRAM_SDQS0 */
-	str	r5, [r1, #0x348] /* DRAM_SDQS1 */
-	str	r6, [r1, #0x34c] /* DRAM_SDQS2 */
-	str	r7, [r1, #0x350] /* DRAM_SDQS3 */
-
-	ldmea	r9!, {r4-r7}
 	str	r4, [r1, #0x5c4] /* GPR_B0DS */
 	str	r5, [r1, #0x5cc] /* GPR_B1DS */
 	str r6, [r1, #0x5d4] /* GPR_B2DS */
@@ -93,11 +84,35 @@
 	str	r6, [r1, #0x33c] /* DRAM_SODT0*/
 	str	r7, [r1, #0x340] /* DRAM_SODT1*/
 
-	ldmea	r9!, {r4-r7}
+	ldmea	r9!, {r4-r6}
 	str	r4, [r1, #0x330] /* DRAM_SDCKE0 */
 	str	r5, [r1, #0x334] /* DRAM_SDCKE1 */
 	str	r6, [r1, #0x320] /* DRAM_RESET */
-	str	r7, [r1, #0x5c8] /* GPR_CTLDS */
+
+	/* Need to reset the FIFO to avoid MMDC lockup
+	  * caused because of floating/changing the
+	  * configuration of many DDR IO pads.
+	  */
+	/* reset read FIFO, RST_RD_FIFO */
+	ldr	r7, =0x83c
+	ldr	r6, [r8, r7]
+	orr	r6, r6, #0x80000000
+	str	r6, [r8, r7]
+fifo_reset1_wait:
+	ldr	r6, [r8, r7]
+	and	r6, r6, #0x80000000
+	cmp	r6, #0
+	bne	fifo_reset1_wait
+
+	/* reset FIFO a second time */
+	ldr	r6, [r8, r7]
+	orr	r6, r6, #0x80000000
+	str	r6, [r8, r7]
+fifo_reset2_wait:
+	ldr	r6, [r8, r7]
+	and	r6, r6, #0x80000000
+	cmp	r6, #0
+	bne	fifo_reset2_wait
 
 	.endm
 
@@ -109,18 +124,6 @@
 	str	r4, [r1, #0x314] /* DRAM_DQM2 */
 	str	r4, [r1, #0x318] /* DRAM_DQM3 */
 
-	/* Make sure the Pull Ups are enabled.
-	 * So only reduce the drive stength, but
-	 * leave the pull-ups in the original state.
-	 * This is required for LPDDR2.
-	 */
-	ldr	r4, [r1, #0x344]
-	orr	r4, r4, #0x3000
-	str	r4, [r1, #0x344] /* DRAM_SDQS0 */
-	str	r4, [r1, #0x348] /* DRAM_SDQS1 */
-	str	r4, [r1, #0x34c] /* DRAM_SDQS2 */
-	str	r4, [r1, #0x350] /* DRAM_SDQS3 */
-
 	str	r4, [r1, #0x5c4] /* GPR_B0DS */
 	str	r4, [r1, #0x5cc] /* GPR_B1DS */
 	str r4, [r1, #0x5d4] /* GPR_B2DS */
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index fb48a3ec94a5..654881af57bd 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -72,7 +72,6 @@
 static struct clk *cpu_clk;
 static struct clk *axi_clk;
 static struct clk *periph_clk;
-static struct clk *axi_org_parent;
 static struct clk *pll3_usb_otg_main_clk;
 
 static struct pm_platform_data *pm_data;
@@ -177,14 +176,10 @@ static void usb_power_up_handler(void)
 }
 
 
-/*
- * For safety, DO NOT define ENABLE_DISP_POWER_GATING for MX6SL EVK.
- * Otherwise will meet PxP processing timeout When run EPDC unit test.
- * The cause is under investigation.
- */
 static void disp_power_down(void)
 {
-#ifdef	ENABLE_DISP_POWER_GATING
+#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
+    !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
 	if (cpu_is_mx6sl()) {
 		__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
 		__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
@@ -206,7 +201,8 @@ static void disp_power_down(void)
 
 static void disp_power_up(void)
 {
-#ifdef	ENABLE_DISP_POWER_GATING
+#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
+    !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
 	if (cpu_is_mx6sl()) {
 		/*
 		 * Need to enable EPDC/LCDIF pix clock, and
@@ -344,9 +340,6 @@ static int mx6_suspend_enter(suspend_state_t state)
 		return -EINVAL;
 	}
 
-	axi_org_parent = clk_get_parent(axi_clk);
-	clk_set_parent(axi_clk, periph_clk);
-
 	if (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY) {
 		if (pm_data && pm_data->suspend_enter)
 			pm_data->suspend_enter();
@@ -363,6 +356,30 @@ static int mx6_suspend_enter(suspend_state_t state)
 		suspend_in_iram(state, (unsigned long)iram_paddr,
 			(unsigned long)suspend_iram_base, cpu_type);
 
+		/* Reset the RBC counter. */
+		/* All interrupts should be masked before the
+		  * RBC counter is reset.
+		 */
+		/* Mask all interrupts. These will be unmasked by
+		  * the mx6_suspend_restore routine below.
+		  */
+		__raw_writel(0xffffffff, gpc_base + 0x08);
+		__raw_writel(0xffffffff, gpc_base + 0x0c);
+		__raw_writel(0xffffffff, gpc_base + 0x10);
+		__raw_writel(0xffffffff, gpc_base + 0x14);
+
+		/* Clear the RBC counter and RBC_EN bit. */
+		/* Disable the REG_BYPASS_COUNTER. */
+		__raw_writel(__raw_readl(MXC_CCM_CCR) &
+			~MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR);
+		/* Make sure we clear REG_BYPASS_COUNT*/
+		__raw_writel(__raw_readl(MXC_CCM_CCR) &
+		(~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR);
+		/* Need to wait for a minimum of 2 CLKILS (32KHz) for the
+		  * counter to clear and reset.
+		  */
+		udelay(80);
+
 		if (arm_pg) {
 			/* restore gic registers */
 			restore_gic_dist_state(0, &gds);
@@ -383,7 +400,6 @@ static int mx6_suspend_enter(suspend_state_t state)
 	} else {
 			cpu_do_idle();
 	}
-	clk_set_parent(axi_clk, axi_org_parent);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index 533d4f5dbfab..6ecd51e9f9ea 100644
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -51,7 +51,7 @@
 extern unsigned int gpc_wake_irq[4];
 
 static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
-static struct clk *ddr_clk;
+extern struct clk *mmdc_ch0_axi;
 
 volatile unsigned int num_cpu_idle;
 volatile unsigned int num_cpu_idle_lock = 0x0;
@@ -86,7 +86,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 
 	int stop_mode = 0;
 	void __iomem *anatop_base = IO_ADDRESS(ANATOP_BASE_ADDR);
-	u32 ccm_clpcr, anatop_val, reg;
+	u32 ccm_clpcr, anatop_val;
 
 	ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
 
@@ -153,8 +153,15 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 	if (stop_mode > 0) {
 		gpc_set_wakeup(gpc_wake_irq);
 		/* Power down and power up sequence */
-		__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET);
-		__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET);
+		/* The PUPSCR counter counts in terms of CLKIL (32KHz) cycles.
+		   * The PUPSCR should include the time it takes for the ARM LDO to
+		   * ramp up.
+		   */
+		__raw_writel(0x202, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET);
+		/* The PDNSCR is a counter that counts in IPG_CLK cycles. This counter
+		  * can be set to minimum values to power down faster.
+		  */
+		__raw_writel(0x101, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET);
 		if (stop_mode >= 2) {
 			/* dormant mode, need to power off the arm core */
 			__raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET);
@@ -198,25 +205,17 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 						HW_ANADIG_REG_2P5);
 				}
 			}
-			/* DL's TO1.0 can't support DSM mode due to ipg glitch */
-			if ((mx6dl_revision() != IMX_CHIP_REVISION_1_0)
-					&& stop_mode != 3)
-				__raw_writel(__raw_readl(MXC_CCM_CCR) |
-					MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR);
-
 			if (stop_mode != 3) {
 				/* Make sure we clear WB_COUNT
 				  * and re-config it.
 				  */
 				__raw_writel(__raw_readl(MXC_CCM_CCR) &
-					(~MXC_CCM_CCR_WB_COUNT_MASK) &
-					(~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR);
-				udelay(80);
-				/* Reconfigurate WB and RBC counter, need to set WB counter
+					(~MXC_CCM_CCR_WB_COUNT_MASK),
+					MXC_CCM_CCR);
+				/* Reconfigure WB, need to set WB counter
 				 * to 0x7 to make sure it work normally */
 				__raw_writel(__raw_readl(MXC_CCM_CCR) |
-					(0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET) |
-					(0x20 << MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET),
+					(0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET),
 					MXC_CCM_CCR);
 
 				/* Set WB_PER enable */
@@ -272,11 +271,9 @@ void arch_idle_single_core(void)
 		ca9_do_idle();
 	} else {
 		if (low_bus_freq_mode || audio_bus_freq_mode) {
-				u32 ddr_usecount;
-				if (ddr_clk == NULL)
-					ddr_clk = clk_get(NULL ,
-								"mmdc_ch0_axi");
-				ddr_usecount = clk_get_usecount(ddr_clk);
+			int ddr_usecount = 0;
+			if ((mmdc_ch0_axi != NULL))
+				ddr_usecount = clk_get_usecount(mmdc_ch0_axi);
 
 			if (cpu_is_mx6sl() && low_bus_freq_mode
 				&& ddr_usecount == 1) {
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index 073c237cc387..eb163abd4f36 100755
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -61,6 +61,16 @@ static int __init jtag_wfi_setup(char *p)
 	return 0;
 }
 early_param("jtag", jtag_wfi_setup);
+
+
+static int __init setup_debug_uart(char *p)
+{
+	uart_at_24 = 1;
+	return 0;
+}
+
+early_param("debug_uart", setup_debug_uart);
+
 /**
  * early_console_setup - setup debugging console
  *
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index a4a15482c71f..b5cfba1a5047 100755
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -722,6 +722,9 @@ void stop_dvfs(void)
 	unsigned long flags;
 	u32 curr_cpu;
 	int cpu;
+#ifndef CONFIG_SMP
+	unsigned long old_loops_per_jiffy;
+#endif
 
 	if (dvfs_core_is_active) {
 
@@ -752,7 +755,7 @@ void stop_dvfs(void)
 				dvfs_cpu_jiffies(per_cpu(cpu_data, cpu).loops_per_jiffy,
 					curr_cpu/1000, clk_get_rate(cpu_clk) / 1000);
 #else
-		u32 old_loops_per_jiffy = loops_per_jiffy;
+		old_loops_per_jiffy = loops_per_jiffy;
 
 		loops_per_jiffy =
 			dvfs_cpu_jiffies(old_loops_per_jiffy,