diff options
| author | Dong Aisheng <b29396@freescale.com> | 2015-06-11 17:01:16 +0800 |
|---|---|---|
| committer | Dong Aisheng <b29396@freescale.com> | 2015-06-11 20:02:12 +0800 |
| commit | 2e4f9e33fd8b77bb29f928a206a8d1a270789a59 (patch) | |
| tree | 1fb5ceaf697d348b680e70ba5d9e5a8650898e58 /arch | |
| parent | c4e8538dac5d63117bbb314f2ffbcbe82e58b4d2 (diff) | |
MLK-11093-2 dts: imx6ul-14x14-ddr3-arm2-emmc: enable HS200 support
Add ultra high speed mode pinctrl states to support eMMC HS200.
HW rework needed that changing both NVCC_SD and NVCC_NAND to 1.8v.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts | 42 |
2 files changed, 40 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts index 234d3ce54aeb..2e35ed6d353e 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2-emmc.dts @@ -9,12 +9,15 @@ #include "imx6ul-14x14-ddr3-arm2.dts" &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1_8bit>; + pinctrl-1 = <&pinctrl_usdhc1_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_8bit_200mhz>; bus-width = <8>; cd-gpios = <>; wp-gpios = <>; vmmc-supply = <>; + tuning-step = <2>; non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts index ace79255141f..d93fd9bafe4d 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-ddr3-arm2.dts @@ -647,12 +647,12 @@ pinctrl_usdhc1_8bit: usdhc1_8bit_grp { fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 @@ -660,6 +660,36 @@ >; }; + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 |