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authorNitin Kumbhar <nkumbhar@nvidia.com>2011-04-25 14:42:58 +0530
committerNitin Kumbhar <nkumbhar@nvidia.com>2011-04-25 14:42:58 +0530
commited22062df7ae836e674c01f69e8567ad51ba31b1 (patch)
tree32972feea81e770d650a3dc7d36907a7c49f9d4d /arch
parent90651aad036485974b99101df66a50e57c19e732 (diff)
parent2e35e1d7b965893e68f2fb1af77129406be5ff05 (diff)
merging android-tegra-2.6.36 into git-master/linux-2.6/android-tegra-2.6.36
Conflicts: arch/arm/mm/proc-v7.S drivers/video/tegra/dc/dc.c Change-Id: I40be0d615f14f1c01305388a706d257f624ba968
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0a293ee4a313..cd2c427f0e2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1129,16 +1129,6 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption of the
processor.
-config ARM_ERRATA_720791
- bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream"
- depends on CPU_V7
- help
- This option enables the workaround for the 720791 Cortex-A9
- (r1p0..r1p2) erratum. The Jazelle instruction stream may be
- corrupted when dynamic high-level clock gating is enabled.
- This workaround disables gating the Core clock when the Instruction
- side is waiting for a Page Table Walk answer or linefill completion.
-
endmenu
source "arch/arm/common/Kconfig"