arm: tegra: cardhu: Update EMC DFS table for Hynix DDR3

Added 900MHz, 850MHz, 450MHz and 425MHz for T33 parts.

Change-Id: I6577b7c1e2242b5c9da2378b074eb40da11fb562
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/83308
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

1 files changed, 480 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu-memory.c b/arch/arm/mach-tegra/board-cardhu-memory.c
index d5419e4c2b23..4b009888d165 100644
--- a/arch/arm/mach-tegra/board-cardhu-memory.c
+++ b/arch/arm/mach-tegra/board-cardhu-memory.c
@@ -1216,6 +1216,246 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 	},
 	{
 		0x32,       /* Rev 3.2 */
+		425000,     /* SDRAM frequency */
+		{
+			0x00000012, /* EMC_RC */
+			0x00000040, /* EMC_RFC */
+			0x0000000d, /* EMC_RAS */
+			0x00000004, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000c, /* EMC_W2P */
+			0x00000004, /* EMC_RD_RCD */
+			0x00000004, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_QRST */
+			0x00000008, /* EMC_QSAFE */
+			0x0000000e, /* EMC_RDV */
+			0x00000c2e, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000008, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000008, /* EMC_AR2PDEN */
+			0x00000011, /* EMC_RW2PDEN */
+			0x00000046, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x0000000a, /* EMC_TCKE */
+			0x0000000d, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000c6f, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x001c0084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00034000, /* EMC_DLL_XFORM_DQS0 */
+			0x00034000, /* EMC_DLL_XFORM_DQS1 */
+			0x00034000, /* EMC_DLL_XFORM_DQS2 */
+			0x00034000, /* EMC_DLL_XFORM_DQS3 */
+			0x00034000, /* EMC_DLL_XFORM_DQS4 */
+			0x00034000, /* EMC_DLL_XFORM_DQS5 */
+			0x00034000, /* EMC_DLL_XFORM_DQS6 */
+			0x00034000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00040000, /* EMC_DLL_XFORM_DQ0 */
+			0x00040000, /* EMC_DLL_XFORM_DQ1 */
+			0x00040000, /* EMC_DLL_XFORM_DQ2 */
+			0x00040000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x017f000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000006, /* MC_EMEM_ARB_CFG */
+			0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
+			0x7547130b, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0x58000000, /* EMC_FBIO_SPARE */
+			0xff00ff88, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80000731, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		450000,     /* SDRAM frequency */
+		{
+			0x00000014, /* EMC_RC */
+			0x00000046, /* EMC_RFC */
+			0x0000000e, /* EMC_RAS */
+			0x00000005, /* EMC_RP */
+			0x00000003, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000c, /* EMC_W2P */
+			0x00000005, /* EMC_RD_RCD */
+			0x00000005, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_QRST */
+			0x0000000a, /* EMC_QSAFE */
+			0x0000000e, /* EMC_RDV */
+			0x00000d76, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000001, /* EMC_PDEX2WR */
+			0x00000009, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000009, /* EMC_AR2PDEN */
+			0x00000011, /* EMC_RW2PDEN */
+			0x0000004d, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x0000000e, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000db6, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x00180084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00022000, /* EMC_DLL_XFORM_DQS0 */
+			0x00022000, /* EMC_DLL_XFORM_DQS1 */
+			0x00022000, /* EMC_DLL_XFORM_DQS2 */
+			0x00022000, /* EMC_DLL_XFORM_DQS3 */
+			0x00022000, /* EMC_DLL_XFORM_DQS4 */
+			0x00022000, /* EMC_DLL_XFORM_DQS5 */
+			0x00022000, /* EMC_DLL_XFORM_DQS6 */
+			0x00022000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00030000, /* EMC_DLL_XFORM_DQ0 */
+			0x00030000, /* EMC_DLL_XFORM_DQ1 */
+			0x00030000, /* EMC_DLL_XFORM_DQ2 */
+			0x00030000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0178000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000006, /* MC_EMEM_ARB_CFG */
+			0x80000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
+			0x70a7150c, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff8b, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80000731, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
 		533000,     /* SDRAM frequency */
 		{
 			0x00000018, /* EMC_RC */
@@ -1574,6 +1814,246 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
 		0x80200018, /* Mode Register 2 */
 		0x00000000, /* EMC_CFG.DYN_SELF_REF */
 	},
+	{
+		0x32,       /* Rev 3.2 */
+		850000,     /* SDRAM frequency */
+		{
+			0x00000028, /* EMC_RC */
+			0x00000086, /* EMC_RFC */
+			0x0000001c, /* EMC_RAS */
+			0x0000000a, /* EMC_RP */
+			0x00000006, /* EMC_R2W */
+			0x0000000f, /* EMC_W2R */
+			0x00000005, /* EMC_R2P */
+			0x00000016, /* EMC_W2P */
+			0x0000000a, /* EMC_RD_RCD */
+			0x0000000a, /* EMC_WR_RCD */
+			0x00000004, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000008, /* EMC_WDV */
+			0x0000000d, /* EMC_QUSE */
+			0x0000000b, /* EMC_QRST */
+			0x0000000b, /* EMC_QSAFE */
+			0x00000014, /* EMC_RDV */
+			0x000019a6, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000669, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000004, /* EMC_PDEX2WR */
+			0x00000013, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000010, /* EMC_AR2PDEN */
+			0x0000001b, /* EMC_RW2PDEN */
+			0x00000091, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000006, /* EMC_TCKE */
+			0x0000001a, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000008, /* EMC_TCLKSTABLE */
+			0x00000009, /* EMC_TCLKSTOP */
+			0x000019e6, /* EMC_TREFBW */
+			0x0000000e, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0xf0050191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0000c00a, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS2 */
+			0x007fc008, /* EMC_DLL_XFORM_DQS3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE1 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE2 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE3 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE4 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE5 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE6 */
+			0x0000c000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x22220000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f501, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000110, /* EMC_ZCAL_WAIT_CNT */
+			0x0134000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80003384, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0x80000099, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000014, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000d, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
+			0x09050202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00190f14, /* MC_EMEM_ARB_DA_COVERS */
+			0x714d2715, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff49, /* EMC_CFG_RSV */
+		},
+		0x00000044, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000f15, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200020, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		900000,     /* SDRAM frequency */
+		{
+			0x0000002a, /* EMC_RC */
+			0x0000008e, /* EMC_RFC */
+			0x0000001e, /* EMC_RAS */
+			0x0000000b, /* EMC_RP */
+			0x00000006, /* EMC_R2W */
+			0x0000000f, /* EMC_W2R */
+			0x00000005, /* EMC_R2P */
+			0x00000016, /* EMC_W2P */
+			0x0000000b, /* EMC_RD_RCD */
+			0x0000000b, /* EMC_WR_RCD */
+			0x00000004, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000008, /* EMC_WDV */
+			0x0000000d, /* EMC_QUSE */
+			0x0000000b, /* EMC_QRST */
+			0x0000000b, /* EMC_QSAFE */
+			0x00000014, /* EMC_RDV */
+			0x00001b2c, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000004, /* EMC_PDEX2WR */
+			0x00000014, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000011, /* EMC_AR2PDEN */
+			0x0000001b, /* EMC_RW2PDEN */
+			0x00000099, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000006, /* EMC_TCKE */
+			0x0000001b, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000008, /* EMC_TCLKSTABLE */
+			0x00000009, /* EMC_TCLKSTOP */
+			0x00001b6c, /* EMC_TREFBW */
+			0x0000000e, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0xf0040191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0000800a, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE1 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE2 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE3 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE4 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE5 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE6 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x22220000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f501, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000120, /* EMC_ZCAL_WAIT_CNT */
+			0x0128000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000d, /* MC_EMEM_ARB_CFG */
+			0x800000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000016, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
+			0x09050202, /* MC_EMEM_ARB_DA_TURNS */
+			0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
+			0x714e2917, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff4b, /* EMC_CFG_RSV */
+		},
+		0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000f15, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200020, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
 };
 
 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {