diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-01-25 22:19:03 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2016-01-28 18:54:28 +0800 |
| commit | 30392c3e0ec794bff4a0dcbd7c300c826f95e89d (patch) | |
| tree | 09074949d9bd0124abc805c70fa7eb5e4a9ccd76 /arch | |
| parent | 69d5543e8dbdd2c4480ae0b2cb4d84deb13ddc94 (diff) | |
MLK-12262-2 ARM: imx: adjust LPDDR2 frequency scale flow for i.MX7D TO1.1
LPDDR2 frequency scale flow needs to be updated for i.MX7D
TO1.1 due to the CKE timing change.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/lpddr3_freq_imx.S | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S index b122f797f2e8..da85b7cee780 100644 --- a/arch/arm/mach-imx/lpddr3_freq_imx.S +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -242,6 +242,20 @@ ldr r7, =0x8 str r7, [r5, #DDRPHY_OFFSETW_CON2] + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + beq 15f + + ldr r7, =0x08080808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON0] + str r7, [r5, #DDRPHY_CA_DSKEW_CON1] + ldr r7, =0x0a0a0808 + str r7, [r5, #DDRPHY_CA_DSKEW_CON2] + ldr r7, =0x0a0a0a0a + str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0] + b 14f +15: ldr r7, [r9, #ANADIG_DIGPROG] and r7, r7, #0x11 cmp r7, #0x10 |