diff options
| author | Lin Fuzhen <fuzhen.lin@freescale.com> | 2012-08-06 16:30:41 +0800 |
|---|---|---|
| committer | Lin Fuzhen <fuzhen.lin@freescale.com> | 2012-08-07 11:18:50 +0800 |
| commit | deae3ebb8ee10ea79b01f0e00b1770cf642b1e23 (patch) | |
| tree | f77fcb97287b89bed5cef5cee6afe9a0f292f5c1 /arch | |
| parent | 511f74fdef926a8e26d5aaa64135a4745a3e65fa (diff) | |
ENGR00219488 mx6q gpu: fix suspend/resume fail issue
For MX6Q GPU2D clock(shared with openVG) source from PLL3_USB_OTG_480M,
so need to enable PLL3 before power up the GPU. Otherwise, GPU will rusume
fail and system will hang when system resume from suspend mode if PLL3
is not ready at that time.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mx6/pm.c | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 61cf37c9a4f8..f21fab4bbe95 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5381,7 +5381,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* Need to keep PLL3_PFD_540M enabled until AXI is sourced from it. */ clk_enable(&axi_clk); - if (cpu_is_mx6q() && (mx6q_revision() > IMX_CHIP_REVISION_1_1)) + if (cpu_is_mx6q()) clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk); clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M); diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c index 50df5714b2d8..b1d91e311b5e 100644 --- a/arch/arm/mach-mx6/pm.c +++ b/arch/arm/mach-mx6/pm.c @@ -205,6 +205,13 @@ static void gpu_power_up(void) __raw_writel(ccm_analog_pfd528 & ~ANADIG_PFD0_CLKGATE & ~ANADIG_PFD1_CLKGATE, PFD_528_BASE_ADDR); + /* make sure PLL3_USB_OTG_480M is enabled for MX6Q + * MX6Q GPU2d_core clock source from PLL3_USB_OTG_480M, + * so need to enable pll3 beofore power up gpu + */ + if (cpu_is_mx6q()) + __raw_writel(ANADIG_PLL_ENABLE|ANADIG_PLL_POWER_DOWN, + (PLL3_480_USB1_BASE_ADDR+4)); /* gpu3d and gpu2d clock enable */ __raw_writel(ccgr1 | MXC_CCM_CCGRx_CG12_MASK | |