[ARM/tegra] ventana ODM: add initial ODM kit for ventana

Change-Id: I01a3cadf3dfeda155ba234e515405f9f2e5ce4fd
Reviewed-on: http://git-master/r/3109
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

21 files changed, 2624 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/odm_kit/Kconfig b/arch/arm/mach-tegra/odm_kit/Kconfig
index 489cd70feaf5..c27bf1a836cc 100644
--- a/arch/arm/mach-tegra/odm_kit/Kconfig
+++ b/arch/arm/mach-tegra/odm_kit/Kconfig
@@ -5,6 +5,10 @@ config TEGRA_ODM_HARMONY
 	bool "NVIDIA Tango or Harmony development system"
 	depends on ARCH_TEGRA_2x_SOC && MACH_TEGRA_GENERIC
 
+config TEGRA_ODM_VENTANA
+	bool "NVIDIA Ventana development system"
+	depends on ARCH_TEGRA_2x_SOC && MACH_TEGRA_GENERIC
+
 config TEGRA_ODM_WHISTLER
 	bool "NVIDIA Whistler development system"
 	depends on ARCH_TEGRA_2x_SOC && MACH_TEGRA_GENERIC
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile
index 61c287105a48..b96894b3d7e4 100644
--- a/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= harmony/
 obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= whistler/
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= ventana/
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/Makefile b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/Makefile
new file mode 100644
index 000000000000..12af02178d7f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/Makefile
@@ -0,0 +1,14 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-$(CONFIG_KEYBOARD_TEGRA)	+= nvodm_kbc.o
+obj-$(CONFIG_KEYBOARD_TEGRA)	+= nvodm_kbc_keymapping.o
+obj-y				+= nvodm_sdio.o
+obj-y				+= nvodm_uart.o
+obj-y				+= nvodm_usbulpi.o
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_kbc.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_kbc.c
new file mode 100644
index 000000000000..e5e23df90dde
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_kbc.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2008-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#include "nvodm_kbc.h"
+
+NvU32 NvOdmKbcFilterKeys(
+    NvU32 *pRows,
+    NvU32 *pCols,
+    NvU32 NumOfKeysPressed)
+{
+    return NumOfKeysPressed;
+}
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c
new file mode 100644
index 000000000000..3179ae75d24e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_sdio.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+#include "nvodm_sdio.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvodm_pmu.h"
+#include "nvos.h"
+
+#define WLAN_GUID   NV_ODM_GUID('s','d','i','o','w','l','a','n')
+
+typedef struct NvOdmSdioRec
+{
+    // NvODM PMU device handle
+    NvOdmServicesPmuHandle hPmu;
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;
+    // Pin handle to Wlan Reset Gpio pin
+    NvOdmGpioPinHandle hResetPin;
+    // Pin handle to Wlan PWR GPIO Pin
+    NvOdmGpioPinHandle hPwrPin;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+    // Power state
+    NvBool PoweredOn;
+    // Instance
+    NvU32 Instance;
+} NvOdmSdio;
+
+static void NvOdmSetPowerOnSdio(NvOdmSdioHandle pDevice, NvBool enable)
+{
+    const NvOdmPeripheralConnectivity *pConn;
+    NvU32 i;
+
+    pConn = pDevice->pConnectivity;
+
+    for (i=0; i<pConn->NumAddress; i++)
+    {
+        const NvOdmIoAddress *addr = &pConn->AddressList[i];
+        NvU32 settle;
+        NvU32 voltage;
+
+        if (addr->Interface != NvOdmIoModule_Vdd)
+            continue;
+
+        if (enable)
+        {
+            NvOdmServicesPmuVddRailCapabilities caps;
+            NvOdmServicesPmuGetCapabilities(pDevice->hPmu, addr->Address, &caps);
+            voltage = caps.requestMilliVolts;
+        }
+        else
+        {
+            voltage = ODM_VOLTAGE_OFF;
+        }
+
+        NvOdmServicesPmuSetVoltage(pDevice->hPmu, addr->Address,
+                                   voltage, &settle);
+
+        if (settle)
+            NvOdmOsWaitUS(settle);
+    }
+}
+
+static NvBool SdioOdmWlanPower(NvOdmSdioHandle hOdmSdio, NvBool IsEnable)
+{
+    if (IsEnable)
+    {
+        // Wlan Power On Reset Sequence
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x0);
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x0);
+        NvOdmOsWaitUS(2000);
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x1);
+        NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hResetPin, 0x1);
+     }
+     else
+     {
+         // Power Off sequence
+         NvOdmGpioSetState(hOdmSdio->hGpio, hOdmSdio->hPwrPin, 0x0);
+     }
+
+    return NV_TRUE;
+}
+
+NvOdmSdioHandle NvOdmSdioOpen(NvU32 Instance)
+{
+    static NvOdmSdio *pDevice = NULL;
+    NvOdmServicesGpioHandle hGpioTemp = NULL;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 NumOfGuids = 1;
+    NvU64 guid;
+    NvU32 searchVals[2];
+    const NvU32 *pOdmConfigs;
+    NvU32 NumOdmConfigs;
+    NvBool Status = NV_TRUE;
+    const NvOdmPeripheralSearch searchAttrs[] =
+    {
+        NvOdmPeripheralSearch_IoModule,
+        NvOdmPeripheralSearch_Instance,
+    };
+
+    searchVals[0] =  NvOdmIoModule_Sdio;
+    searchVals[1] =  Instance;
+
+    NvOdmQueryPinMux(NvOdmIoModule_Sdio, &pOdmConfigs, &NumOdmConfigs);
+    if (Instance >= NumOdmConfigs )
+        return NULL;
+    if( pOdmConfigs[Instance] == 0 )
+        return NULL;
+
+    NumOfGuids = NvOdmPeripheralEnumerate(searchAttrs, searchVals,
+                                          2, &guid, NumOfGuids);
+
+
+    // Get the peripheral connectivity information
+    pConnectivity = NvOdmPeripheralGetGuid(guid);
+    if (pConnectivity == NULL)
+        return NULL;
+
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmSdio));
+    pDevice->hPmu = NULL;
+    if(pDevice == NULL)
+        return (pDevice);
+
+    if (pDevice->hPmu == NULL)
+    {
+        pDevice->hPmu = NvOdmServicesPmuOpen();
+        if(pDevice->hPmu == NULL)
+        {
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (NULL);
+        }
+    }
+
+    pDevice->pConnectivity = pConnectivity;
+    NvOdmSetPowerOnSdio(pDevice, NV_TRUE);
+
+    if (pConnectivity->Guid == WLAN_GUID)
+    {
+        // Getting the OdmGpio Handle
+        hGpioTemp = NvOdmGpioOpen();
+        if (hGpioTemp == NULL)
+        {
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (pDevice);
+        }
+
+        // Search for the Vdd rail and set the proper volage to the rail.
+        if (pConnectivity->AddressList[1].Interface == NvOdmIoModule_Gpio)
+        {
+             // Acquiring Pin Handles for Power Pin
+             pDevice->hPwrPin= NvOdmGpioAcquirePinHandle(hGpioTemp,
+                   pConnectivity->AddressList[1].Instance,
+                   pConnectivity->AddressList[1].Address);
+        }
+
+        if (pConnectivity->AddressList[2].Interface == NvOdmIoModule_Gpio)
+        {
+             // Acquiring Pin Handles for Reset Pin
+             pDevice->hResetPin= NvOdmGpioAcquirePinHandle(hGpioTemp,
+                   pConnectivity->AddressList[2].Instance,
+                   pConnectivity->AddressList[2].Address);
+        }
+
+        // Setting the ON/OFF pin to output mode.
+        NvOdmGpioConfig(hGpioTemp, pDevice->hPwrPin, NvOdmGpioPinMode_Output);
+        NvOdmGpioConfig(hGpioTemp, pDevice->hResetPin, NvOdmGpioPinMode_Output);
+
+        // Setting the Output Pin to Low
+        NvOdmGpioSetState(hGpioTemp, pDevice->hPwrPin, 0x0);
+        NvOdmGpioSetState(hGpioTemp, pDevice->hResetPin, 0x0);
+
+        pDevice->hGpio = hGpioTemp;
+
+        Status = SdioOdmWlanPower(pDevice, NV_TRUE);
+        if (Status != NV_TRUE)
+        {
+            NvOdmOsFree(pDevice);
+            pDevice = NULL;
+            return (pDevice);
+        }
+    }
+    pDevice->PoweredOn = NV_TRUE;
+    pDevice->Instance = Instance;
+    return pDevice;
+}
+
+void NvOdmSdioClose(NvOdmSdioHandle hOdmSdio)
+{
+    if (hOdmSdio->pConnectivity->Guid == WLAN_GUID)
+    {
+        // Call Turn off power when close is Called
+        (void)SdioOdmWlanPower(hOdmSdio, NV_FALSE);
+
+        NvOdmGpioReleasePinHandle(hOdmSdio->hGpio, hOdmSdio->hPwrPin);
+        NvOdmGpioReleasePinHandle(hOdmSdio->hGpio, hOdmSdio->hResetPin);
+        NvOdmGpioClose(hOdmSdio->hGpio);
+    }
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_FALSE);
+    if (hOdmSdio->hPmu != NULL)
+    {
+         NvOdmServicesPmuClose(hOdmSdio->hPmu);
+    }
+    NvOdmOsFree(hOdmSdio);
+    hOdmSdio = NULL;
+}
+
+
+NvBool NvOdmSdioSuspend(NvOdmSdioHandle hOdmSdio)
+{
+    NvBool Status = NV_TRUE;
+
+    if (!hOdmSdio->PoweredOn)
+        return NV_TRUE;
+
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_FALSE);
+
+    if (hOdmSdio->pConnectivity->Guid == WLAN_GUID)
+        Status = SdioOdmWlanPower(hOdmSdio, NV_FALSE);
+
+    hOdmSdio->PoweredOn = NV_FALSE;
+    return Status;
+
+}
+
+NvBool NvOdmSdioResume(NvOdmSdioHandle hOdmSdio)
+{
+    NvBool Status = NV_TRUE;
+
+    if (hOdmSdio->PoweredOn)
+        return NV_TRUE;
+
+    NvOdmSetPowerOnSdio(hOdmSdio, NV_TRUE);
+
+    if (hOdmSdio->pConnectivity->Guid == WLAN_GUID)
+        Status = SdioOdmWlanPower(hOdmSdio, NV_TRUE);
+
+    hOdmSdio->PoweredOn = NV_TRUE;
+    return Status;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_uart.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_uart.c
new file mode 100644
index 000000000000..98a0a6456c91
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_uart.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file          nvodm_uart.c
+ * @brief         <b>Adaptation for uart </b>
+ *
+ * @Description : Implementation of the uart adaptation.
+ */
+#include "nvodm_uart.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvos.h"
+#include "nvodm_pmu.h"
+
+#ifdef NV_DRIVER_DEBUG
+    #define NV_DRIVER_TRACE NvOsDebugPrintf
+#else
+    #define NV_DRIVER_TRACE (void)
+#endif
+
+typedef struct NvOdmUartRec
+{
+    // NvODM PMU device handle
+    NvOdmServicesPmuHandle hPmu;
+    // Gpio Handle
+    NvOdmServicesGpioHandle hGpio;
+    // Pin handle to Bluetooth Reset Gpio pin
+    NvOdmGpioPinHandle hResetPin;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+} NvOdmUart;
+
+NvOdmUartHandle NvOdmUartOpen(NvU32 Instance)
+{
+    NvOdmUart *pDevice = NULL;
+    const NvOdmPeripheralConnectivity *pConnectivity;
+    NvU32 NumOfGuids = 1;
+    NvU64 guid;
+    NvU32 searchVals[2];
+    const NvOdmPeripheralSearch searchAttrs[] =
+    {
+        NvOdmPeripheralSearch_IoModule,
+        NvOdmPeripheralSearch_Instance,
+    };
+
+    searchVals[0] =  NvOdmIoModule_Uart;
+    searchVals[1] =  Instance;
+
+    NumOfGuids =
+        NvOdmPeripheralEnumerate(searchAttrs, searchVals,
+                                 2, &guid, NumOfGuids);
+
+    pConnectivity = NvOdmPeripheralGetGuid(guid);
+    if (pConnectivity == NULL)
+        goto ExitUartOdm;
+
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmUart));
+    if(pDevice == NULL)
+        goto ExitUartOdm;
+
+    pDevice->hPmu = NvOdmServicesPmuOpen();
+    if(pDevice->hPmu == NULL)
+    {
+        goto ExitUartOdm;
+    }
+
+    // Switch On UART Interface
+
+    pDevice->pConnectivity = pConnectivity;
+    return pDevice;
+
+ExitUartOdm:
+    NvOdmOsFree(pDevice);
+    pDevice = NULL;
+    return NULL;
+}
+
+void NvOdmUartClose(NvOdmUartHandle hOdmUart)
+{
+
+    if (hOdmUart)
+    {
+        // Switch OFF UART Interface
+
+        if (hOdmUart->hPmu != NULL)
+        {
+            NvOdmServicesPmuClose(hOdmUart->hPmu);
+        }
+        NvOdmOsFree(hOdmUart);
+        hOdmUart = NULL;
+    }
+}
+
+NvBool NvOdmUartSuspend(NvOdmUartHandle hOdmUart)
+{
+    return NV_FALSE;
+}
+
+NvBool NvOdmUartResume(NvOdmUartHandle hOdmUart)
+{
+    return NV_FALSE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_usbulpi.c b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_usbulpi.c
new file mode 100644
index 000000000000..f6e5804bb988
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/misc/ventana/nvodm_usbulpi.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file          nvodm_usbulpi.c
+ * @brief         <b>Adaptation for USB ULPI </b>
+ *
+ * @Description : Implementation of the USB ULPI adaptation.
+ */
+#include "nvodm_usbulpi.h"
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_services.h"
+#include "nvos.h"
+
+#define SMSC3317GUID NV_ODM_GUID('s','m','s','c','3','3','1','7')
+
+#define MAX_CLOCKS 3
+
+#define NVODM_PORT(x) ((x) - 'a')
+
+
+typedef struct NvOdmUsbUlpiRec
+{
+     NvU64    CurrentGUID;
+} NvOdmUsbUlpi;
+
+NvOdmUsbUlpiHandle NvOdmUsbUlpiOpen(NvU32 Instance)
+{
+    NvOdmUsbUlpi *pDevice = NULL;
+    NvU32 ClockInstances[MAX_CLOCKS];
+    NvU32 ClockFrequencies[MAX_CLOCKS];
+    NvU32 NumClocks;
+    NvOdmServicesGpioHandle hGpio;
+    NvOdmGpioPinHandle hResetPin;
+    NvU32 Port = NVODM_PORT('v');
+    NvU32 Pin = 1;
+
+    pDevice = NvOdmOsAlloc(sizeof(NvOdmUsbUlpi));
+    if (pDevice == NULL)
+        return NULL;
+
+    if(!NvOdmExternalClockConfig(SMSC3317GUID, NV_FALSE,
+                                 ClockInstances, ClockFrequencies, &NumClocks))
+    {
+        NvOdmOsDebugPrintf("NvOdmUsbUlpiOpen: NvOdmExternalClockConfig fail\n");
+        goto ExitUlpiOdm;
+    }
+    NvOdmOsSleepMS(10);
+    // Pull high on RESETB ( 22nd pin of smsc3315)
+    hGpio = NvOdmGpioOpen();
+    hResetPin = NvOdmGpioAcquirePinHandle(hGpio, Port, Pin);
+    // config as out put pin
+    NvOdmGpioConfig(hGpio,hResetPin, NvOdmGpioPinMode_Output);
+    // Set low to write high on ULPI_RESETB pin
+    NvOdmGpioSetState(hGpio, hResetPin, 0x01);
+    NvOdmGpioSetState(hGpio, hResetPin, 0x0);
+    NvOdmOsSleepMS(5);
+    NvOdmGpioSetState(hGpio, hResetPin, 0x01);
+
+    pDevice->CurrentGUID = SMSC3317GUID;
+    return pDevice;
+
+ExitUlpiOdm:
+    NvOdmOsFree(pDevice);
+    return NULL;
+}
+
+void NvOdmUsbUlpiClose(NvOdmUsbUlpiHandle hOdmUlpi)
+{
+    if (hOdmUlpi)
+    {
+        NvOdmOsFree(hOdmUlpi);
+        hOdmUlpi = NULL;
+    }
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile
index 44d31d624e1e..125e37f89ac9 100644
--- a/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/platform/accelerometer/Makefile
@@ -12,4 +12,7 @@ obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_accelerometer_adi340.o
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_priv_accelerometer.o
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_accelerometer_bma150.o
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_accelerometer_kxtf9.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_priv_accelerometer.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_accelerometer_bma150.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_accelerometer_kxtf9.o
 
diff --git a/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile b/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile
index 9c1a4b43b4ab..9494d32754cc 100644
--- a/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/platform/battery/Makefile
@@ -9,3 +9,4 @@ endif
 
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_battery.o
 obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_battery_stub.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_battery_stub.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile b/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile
index 8f6e46d214c6..ed74f8aef03a 100644
--- a/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/platform/keyboard/Makefile
@@ -10,3 +10,4 @@ endif
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_keyboard.o
 obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_keyboard_stub.o
 obj-$(CONFIG_TEGRA_ODM_CONCORDE)	+= nvodm_keyboard_stub.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_keyboard_stub.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile b/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile
index a8897024bf2c..52b44831e429 100644
--- a/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/platform/mouse/Makefile
@@ -8,3 +8,4 @@ ccflags-y += -DNV_DEBUG=0
 endif
 
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_mouse.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_mouse.o
diff --git a/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile
index 071c1f60cc28..4223094e2a7c 100644
--- a/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/platform/scrollwheel/Makefile
@@ -10,3 +10,4 @@ endif
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= nvodm_scrollwheel_stub.o
 obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= nvodm_scrollwheel.o
 obj-$(CONFIG_TEGRA_ODM_CONCORDE)	+= nvodm_scrollwheel.o
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= nvodm_scrollwheel_stub.o
\ No newline at end of file
diff --git a/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile b/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile
index 457bacd20c8c..5c1f5ce3cf4a 100644
--- a/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/platform/touch/Makefile
@@ -19,6 +19,10 @@ ifeq ($(CONFIG_TEGRA_ODM_HARMONY),y)
   is_panjit_touch := y
 endif
 
+ifeq ($(CONFIG_TEGRA_ODM_VENTANA),y)
+  is_panjit_touch := y
+endif
+
 ccflags-$(is_tpk_touch) += -DNV_TOUCH_TPK
 ccflags-$(is_panjit_touch) += -DNV_TOUCH_PANJIT
 
diff --git a/arch/arm/mach-tegra/odm_kit/query/Makefile b/arch/arm/mach-tegra/odm_kit/query/Makefile
index ef54c3faed47..b36c10285d4a 100644
--- a/arch/arm/mach-tegra/odm_kit/query/Makefile
+++ b/arch/arm/mach-tegra/odm_kit/query/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_TEGRA_ODM_HARMONY)		+= harmony/
+obj-$(CONFIG_TEGRA_ODM_VENTANA)		+= ventana/
 obj-$(CONFIG_TEGRA_ODM_WHISTLER)	+= whistler/
 
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/Makefile b/arch/arm/mach-tegra/odm_kit/query/ventana/Makefile
new file mode 100644
index 000000000000..8b24d0ebd270
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/Makefile
@@ -0,0 +1,18 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+
+obj-y += nvodm_query.o
+obj-y += nvodm_query_discovery.o
+obj-y += nvodm_query_gpio.o
+obj-y += nvodm_query_pinmux.o
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query.c
new file mode 100644
index 000000000000..73a536f6ff63
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query.c
@@ -0,0 +1,539 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_query_memc.h"
+#include "nvodm_query_nand.h"
+#include "nvodm_query_kbc.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query_pins.h"
+#include "nvodm_query_pins_ap20.h"
+#include "nvrm_drf.h"
+
+// Wake Events
+static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] =
+{
+    {NV_FALSE,  0, NvOdmWakeupPadPolarity_Low},     // Wake Event  0 - ulpi_data4 (UART_RI)
+    {NV_FALSE,  1, NvOdmWakeupPadPolarity_High},    // Wake Event  1 - gp3_pv[3] (BB_MOD, MODEM_RESET_OUT)
+    {NV_FALSE,  2, NvOdmWakeupPadPolarity_High},    // Wake Event  2 - dvi_d3
+    {NV_FALSE,  3, NvOdmWakeupPadPolarity_Low},     // Wake Event  3 - sdio3_dat1
+    {NV_FALSE,  4, NvOdmWakeupPadPolarity_High},    // Wake Event  4 - hdmi_int (HDMI_HPD)
+    {NV_TRUE,   5, NvOdmWakeupPadPolarity_Low},      // Wake Event  5 - vgp[6] (VI_GP6, Flash_EN2)
+    {NV_FALSE,  6, NvOdmWakeupPadPolarity_High},    // Wake Event  6 - gp3_pu[5] (Lid On/Off)
+    {NV_FALSE,  7, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  7 - gp3_pu[6] (GPS_INT, BT_IRQ)
+    {NV_FALSE,  8, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  8 - gmi_wp_n (MICRO SD_CD)
+    {NV_FALSE,  9, NvOdmWakeupPadPolarity_High},    // Wake Event  9 - gp3_ps[2] (KB_COL10)
+    {NV_FALSE, 10, NvOdmWakeupPadPolarity_High},    // Wake Event 10 - gmi_ad21 (Accelerometer_TH/TAP)
+    {NV_TRUE,  11, NvOdmWakeupPadPolarity_Low},     // Wake Event 11 - spi2_cs2 (PEN_INT, AUDIO-IRQ, LOW_BAT#)
+    {NV_FALSE, 12, NvOdmWakeupPadPolarity_Low},     // Wake Event 12 - spi2_cs1 (HEADSET_DET, not used)
+    {NV_FALSE, 13, NvOdmWakeupPadPolarity_Low},     // Wake Event 13 - sdio1_dat1
+    {NV_FALSE, 14, NvOdmWakeupPadPolarity_High},    // Wake Event 14 - gp3_pv[6] (WLAN_INT)
+    {NV_FALSE, 15, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 15 - gmi_ad16  (SPI3_DOUT, DTV_SPI4_CS1)
+    {NV_FALSE, 16, NvOdmWakeupPadPolarity_High},    // Wake Event 16 - rtc_irq
+    {NV_FALSE,  17, NvOdmWakeupPadPolarity_High},    // Wake Event 17 - kbc_interrupt
+    {NV_FALSE, 18, NvOdmWakeupPadPolarity_Low},     // Wake Event 18 - pwr_int (PMIC_INT)
+    {NV_TRUE, 19, NvOdmWakeupPadPolarity_High},    // Wake Event 19 - usb_vbus_wakeup[0]
+    {NV_FALSE, 20, NvOdmWakeupPadPolarity_High},    // Wake Event 20 - usb_vbus_wakeup[1]
+    {NV_FALSE, 21, NvOdmWakeupPadPolarity_Low},     // Wake Event 21 - usb_iddig[0]
+    {NV_FALSE, 22, NvOdmWakeupPadPolarity_Low},     // Wake Event 22 - usb_iddig[1]
+    {NV_FALSE, 23, NvOdmWakeupPadPolarity_Low},     // Wake Event 23 - gmi_iordy (HSMMC_CLK)
+    {NV_FALSE, 24, NvOdmWakeupPadPolarity_High},    // Wake Event 24 - gp3_pv[2] (power key on gpio  port v2)
+    {NV_FALSE, 25, NvOdmWakeupPadPolarity_High},    // Wake Event 25 - gp3_ps[4] (KB_COL12)
+    {NV_FALSE, 26, NvOdmWakeupPadPolarity_High},    // Wake Event 26 - gp3_ps[5] (KB_COL10)
+    {NV_FALSE, 27, NvOdmWakeupPadPolarity_High},    // Wake Event 27 - gp3_ps[0] (KB_COL8)
+    {NV_FALSE, 28, NvOdmWakeupPadPolarity_Low},     // Wake Event 28 - gp3_pq[6] (KB_ROW6)
+    {NV_FALSE, 29, NvOdmWakeupPadPolarity_Low},     // Wake Event 29 - gp3_pq[7] (KB_ROW6)
+    {NV_FALSE, 30, NvOdmWakeupPadPolarity_High}     // Wake Event 30 - dap1_dout (DAP1_DOUT)
+};
+
+/* --- Function Implementations ---*/
+NvOdmDebugConsole NvOdmQueryDebugConsole(void)
+{
+    return NvOdmDebugConsole_UartD;
+}
+
+NvOdmDownloadTransport NvOdmQueryDownloadTransport(void)
+{
+    return NvOdmDownloadTransport_None;
+}
+
+const NvU8* NvOdmQueryDeviceNamePrefix(void)
+{
+    return (const NvU8 *) "Tegra";
+}
+
+const NvOdmQuerySpiDeviceInfo *NvOdmQuerySpiGetDeviceInfo(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 ChipSelect)
+{
+    static const NvOdmQuerySpiDeviceInfo spi0_cs0 =
+        { NvOdmQuerySpiSignalMode_0, NV_TRUE, NV_FALSE, NV_FALSE, 0, 0 };
+
+    if (Module==NvOdmIoModule_Spi && Instance==0 && ChipSelect==0)
+        return &spi0_cs0;
+
+    return NULL;
+}
+
+const NvOdmQuerySpiIdleSignalState *NvOdmQuerySpiGetIdleSignalState(
+    NvOdmIoModule Module,
+    NvU32 Instance)
+{
+    static const NvOdmQuerySpiIdleSignalState spi[] =
+    {
+        { NV_FALSE, NvOdmQuerySpiSignalMode_0, NV_FALSE },
+    };
+
+    if (Module != NvOdmIoModule_Spi)
+        return NULL;
+
+    if (Instance >= NV_ARRAY_SIZE(spi))
+        return NULL;
+
+    return &spi[Instance];
+}
+
+const NvOdmQueryI2sInterfaceProperty *NvOdmQueryI2sGetInterfaceProperty(
+    NvU32 Instance)
+{
+    static const NvOdmQueryI2sInterfaceProperty i2s[] =
+    {
+        {
+            NvOdmQueryI2sMode_Master,
+            NvOdmQueryI2sLRLineControl_LeftOnLow,
+            NvOdmQueryI2sDataCommFormat_I2S,
+            NV_FALSE, 0
+        },
+        {
+            NvOdmQueryI2sMode_Master,
+            NvOdmQueryI2sLRLineControl_LeftOnLow,
+            NvOdmQueryI2sDataCommFormat_I2S,
+            NV_FALSE, 0
+        }
+    };
+
+    if (Instance >= NV_ARRAY_SIZE(i2s))
+        return NULL;
+
+    return &i2s[Instance];
+}
+
+const NvOdmQueryDapPortProperty *NvOdmQueryDapPortGetProperty(NvU32 Instance)
+{
+    static const NvOdmQueryDapPortProperty dap[] =
+    {
+        { NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Reserved
+
+        // I2S1 (DAC1) <-> DAP1 <-> HIFICODEC
+        {
+            NvOdmDapPort_I2s1, NvOdmDapPort_HifiCodecType,
+            { 2, 16, 44100, NvOdmQueryI2sDataCommFormat_I2S }
+        },
+
+        { NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Dap2
+        { NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Dap3
+
+        // I2S2 (DAC2) <-> DAP4 <-> BLUETOOTH
+        {
+            NvOdmDapPort_I2s2, NvOdmDapPort_BlueTooth,
+            { 2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S }
+        }
+    };
+
+    if (Instance && Instance<NV_ARRAY_SIZE(dap))
+        return &dap[Instance];
+
+    return NULL;
+}
+
+const NvOdmQueryDapPortConnection *NvOdmQueryDapPortGetConnectionTable(
+    NvU32 Index)
+{
+    static const NvOdmQueryDapPortConnection connect[] =
+    {
+        // the Default Music Path
+        { 
+            NvOdmDapConnectionIndex_Music_Path, 2,
+            {
+                { NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_TRUE },
+                { NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_FALSE }
+            }
+        },
+
+        // Bluetooth to Codec
+        {
+            NvOdmDapConnectionIndex_BlueTooth_Codec, 3,
+            {
+                { NvOdmDapPort_Dap4, NvOdmDapPort_I2s1, NV_TRUE },
+                { NvOdmDapPort_I2s1, NvOdmDapPort_Dap4, NV_FALSE },
+                { NvOdmDapPort_I2s2, NvOdmDapPort_Dap1, NV_FALSE }
+            }
+        }
+    };
+
+    NvU32 i = 0;
+    for(i = 0; i < NV_ARRAY_SIZE(connect); i++)
+    {
+        if (connect[i].UseIndex == Index)
+            return &connect[i];
+    }
+    return NULL;
+}
+
+const NvOdmQuerySpdifInterfaceProperty *NvOdmQuerySpdifGetInterfaceProperty(
+    NvU32 Instance)
+{
+    static const NvOdmQuerySpdifInterfaceProperty spdif =
+        { NvOdmQuerySpdifDataCaptureControl_FromLeft };
+
+    return (Instance == 0) ? &spdif : NULL;
+}
+
+const NvOdmQueryAc97InterfaceProperty *NvOdmQueryAc97GetInterfaceProperty(
+    NvU32 Instance)
+{
+    static const NvOdmQueryAc97InterfaceProperty ac97 =
+        { NV_FALSE, NV_FALSE, NV_FALSE, NV_FALSE, NV_TRUE };
+
+    return (Instance == 0) ? &ac97 : NULL;
+}
+
+const NvOdmQueryI2sACodecInterfaceProp *NvOdmQueryGetI2sACodecInterfaceProperty(
+    NvU32 Instance)
+{
+    static const NvOdmQueryI2sACodecInterfaceProp i2s_codec[] =
+    {
+        {
+            NV_FALSE, 0, 0x36, NV_FALSE,
+            NvOdmQueryI2sLRLineControl_LeftOnLow,
+            NvOdmQueryI2sDataCommFormat_I2S
+        },
+    };
+
+    if (Instance < NV_ARRAY_SIZE(i2s_codec))
+        return &i2s_codec[Instance];
+
+    return NULL;
+}
+
+/**
+ * This function is called from early boot process.
+ * Therefore, it cannot use global variables.
+ */
+NvBool NvOdmQueryAsynchMemConfig(
+    NvU32 ChipSelect,
+    NvOdmAsynchMemConfig *pMemConfig)
+{
+    return NV_FALSE;
+}
+
+const void* NvOdmQuerySdramControllerConfigGet(
+    NvU32 *pEntries,
+    NvU32 *pRevision)
+{
+    if (pEntries)
+        *pEntries = 0;
+    return NULL;
+}
+
+NvOdmQueryOscillator NvOdmQueryGetOscillatorSource(void)
+{
+    return NvOdmQueryOscillator_Xtal;
+}
+
+NvU32 NvOdmQueryGetOscillatorDriveStrength(void)
+{
+    /// Oscillator drive strength range is 0 to 0x3F
+    return 0x04;
+}
+
+const NvOdmWakeupPadInfo *NvOdmQueryGetWakeupPadTable(NvU32 *pSize)
+{
+    if (pSize)
+        *pSize = NV_ARRAY_SIZE(s_NvOdmWakeupPadInfo);
+
+    return (const NvOdmWakeupPadInfo *) s_NvOdmWakeupPadInfo;
+}
+
+const NvU8* NvOdmQueryManufacturer(void)
+{
+    return (const NvU8 *) "NVIDIA";
+}
+
+const NvU8* NvOdmQueryModel(void)
+{
+    return (const NvU8 *) "AP20";
+}
+
+const NvU8* NvOdmQueryPlatform(void)
+{
+    return (const NvU8 *) "Ventana";
+}
+
+const NvU8* NvOdmQueryProjectName(void)
+{
+    return (const NvU8 *) "ODM Kit";
+}
+
+#define EXT 0     // external pull-up/down resistor
+#define INT_PU 1  // internal pull-up
+#define INT_PD 2  // internal pull-down
+
+#define HIGHSPEED 1
+#define SCHMITT 1
+#define VREF    1
+#define OHM_50 3
+#define OHM_100 2
+#define OHM_200 1
+#define OHM_400 0
+
+ // Pin attributes
+static const NvOdmPinAttrib pin_config[] = {
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_B,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) },
+
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_E,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x2, 0x2) },
+
+    // Set pad control for the sdio2 - - AOCFG1 and AOCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio3 - SDIO2 and SDIO3 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO2CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO3CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C1 pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DBGCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C2 (DDC) pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DDCCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio1 - SDIO1 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO1CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+     // WiFi Pins (DTA, DTD) need to be pulled up
+    { NvOdmPinRegister_Ap20_PullUpDown_A,
+      NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0) },
+
+    // Set pad control for the sdio4- ATCCFG1 and ATCCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) }
+};
+
+NvU32
+NvOdmQueryPinAttributes(const NvOdmPinAttrib** pPinAttributes)
+{
+    if (pPinAttributes)
+    {
+        *pPinAttributes = &pin_config[0];
+        return NV_ARRAY_SIZE(pin_config);
+    }
+    return 0;
+}
+
+NvBool NvOdmQueryGetPmuProperty(NvOdmPmuProperty* pPmuProperty)
+{
+    pPmuProperty->IrqConnected = NV_FALSE;
+    pPmuProperty->PowerGoodCount = 0x7E7E;
+    pPmuProperty->IrqPolarity = NvOdmInterruptPolarity_Low;
+    pPmuProperty->CorePowerReqPolarity = NvOdmCorePowerReqPolarity_Low;
+    pPmuProperty->SysClockReqPolarity = NvOdmSysClockReqPolarity_High;
+    pPmuProperty->CombinedPowerReq = NV_FALSE;
+    pPmuProperty->CpuPowerGoodUs = 2000;
+    pPmuProperty->AccuracyPercent = 3;
+    pPmuProperty->VCpuOTPOnWakeup = NV_FALSE;
+    pPmuProperty->PowerOffCount = 0;
+    pPmuProperty->CpuPowerOffUs = 0;
+    return NV_TRUE;
+}
+
+/**
+ * Gets the lowest soc power state supported by the hardware
+ *
+ * @returns information about the SocPowerState
+ */
+const NvOdmSocPowerStateInfo* NvOdmQueryLowestSocPowerState(void)
+{
+    static const NvOdmSocPowerStateInfo Info =
+        { NvOdmSocPowerState_Suspend, 525 };
+
+    return &Info;
+}
+
+const NvOdmUsbProperty *NvOdmQueryGetUsbProperty(
+    NvOdmIoModule Module,
+    NvU32 Instance)
+{
+    static const NvOdmUsbProperty usb[] =
+    {
+        {
+            NvOdmUsbInterfaceType_Utmi,
+            (NvOdmUsbChargerType_SE0 | NvOdmUsbChargerType_SE1 |
+             NvOdmUsbChargerType_SK),
+            20, NV_TRUE, NvOdmUsbModeType_Device, NvOdmUsbIdPinType_CableId,
+            NvOdmUsbConnectorsMuxType_None, NV_TRUE, { 0, 0, 0, 0 }
+        },
+        {
+            NvOdmUsbInterfaceType_UlpiExternalPhy,
+            NvOdmUsbChargerType_UsbHost,
+            20, NV_TRUE, NvOdmUsbModeType_Host, NvOdmUsbIdPinType_None,
+            NvOdmUsbConnectorsMuxType_None, NV_TRUE, { 0, 0, 0, 0 }
+        },
+        {
+            NvOdmUsbInterfaceType_Utmi,
+            NvOdmUsbChargerType_UsbHost,
+            20, NV_TRUE, NvOdmUsbModeType_Host, NvOdmUsbIdPinType_None,
+            NvOdmUsbConnectorsMuxType_None, NV_TRUE, { 0, 0, 0, 0 }
+        },
+    };
+
+    if (Module != NvOdmIoModule_Usb || Instance >= NV_ARRAY_SIZE(usb))
+        return NULL;
+
+    return &usb[Instance];
+}
+
+const NvOdmQuerySdioInterfaceProperty* NvOdmQueryGetSdioInterfaceProperty(
+    NvU32 Instance)
+{
+    static const NvOdmQuerySdioInterfaceProperty sdio[] =
+    {
+        { NV_FALSE, 10, NV_TRUE, 0x8, NvOdmQuerySdioSlotUsage_wlan   },
+        { NV_FALSE,  0, NV_FALSE, 0, NvOdmQuerySdioSlotUsage_unused  },
+        { NV_TRUE,   0, NV_FALSE, 0x6, NvOdmQuerySdioSlotUsage_Media },
+        { NV_FALSE,  0, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_Boot  },
+    };
+
+    if (Instance < NV_ARRAY_SIZE(sdio))
+        return &sdio[Instance];
+
+    return NULL;
+}
+
+const NvOdmQueryHsmmcInterfaceProperty* NvOdmQueryGetHsmmcInterfaceProperty(
+    NvU32 Instance)
+{
+    return NULL;
+}
+
+NvU32 NvOdmQueryGetBlockDeviceSectorSize(NvOdmIoModule OdmIoModule)
+{
+    return 0;
+}
+
+const NvOdmQueryOwrDeviceInfo* NvOdmQueryGetOwrDeviceInfo(NvU32 Instance)
+{
+    return NULL;
+}
+
+const NvOdmGpioWakeupSource *NvOdmQueryGetWakeupSources(NvU32 *pCount)
+{
+    *pCount = 0;
+    return NULL;
+}
+
+NvU32 NvOdmQueryMemSize(NvOdmMemoryType MemType)
+{
+    switch (MemType)
+    {
+    case NvOdmMemoryType_Sdram:
+        return 0x40000000;
+    case NvOdmMemoryType_Nor:
+    case NvOdmMemoryType_Nand:
+    case NvOdmMemoryType_I2CEeprom:
+    case NvOdmMemoryType_Hsmmc:
+    case NvOdmMemoryType_Mio:
+    default:
+        return 0;
+    }
+}
+
+NvU32 NvOdmQueryCarveoutSize(void)
+{
+    return 0x08000000; // 128 MB
+}
+
+NvU32 NvOdmQuerySecureRegionSize(void)
+{
+    return 0;
+}
+NvOdmNandFlashParams *NvOdmNandGetFlashInfo (NvU32 ReadID)
+{
+    return NULL;
+}
+
+void NvOdmKbcGetParameter(
+    NvOdmKbcParameter Param,
+    NvU32 SizeOfValue,
+    void * pValue)
+{
+}
+
+NvU32 NvOdmKbcGetKeyCode(
+    NvU32 Row,
+    NvU32 Column,
+    NvU32 RowCount,
+    NvU32 ColumnCount)
+{
+    return 0;
+}
+
+NvBool NvOdmKbcIsSelectKeysWkUpEnabled(
+    NvU32 **pRowNumber,
+    NvU32 **pColNumber,
+    NvU32 *NumOfKeys)
+{
+    return NV_FALSE;
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_discovery.c b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_discovery.c
new file mode 100644
index 000000000000..274977c7ded7
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_discovery.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_modules.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query.h"
+#include "nvrm_drf.h"
+
+#include "subboards/nvodm_query_discovery_pm275_addresses.h"
+
+static NvOdmPeripheralConnectivity s_Peripherals_Default[] =
+{
+#include "subboards/nvodm_query_discovery_pm275_peripherals.h"
+};
+
+NvBool NvOdmPeripheralGetBoardInfo(
+    NvU16 BoardId,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    pBoardInfo = NULL;
+    return NV_FALSE;
+}
+
+static const NvOdmPeripheralConnectivity *NvApGetAllPeripherals(NvU32 *pNum)
+{
+    *pNum = NV_ARRAY_SIZE(s_Peripherals_Default);
+    return s_Peripherals_Default;
+}
+
+// This implements a simple linear search across the entire set of currently-
+// connected peripherals to find the set of GUIDs that Match the search
+// criteria.  More clever implementations are possible, but given the
+// relatively small search space (max dozens of peripherals) and the relative
+// infrequency of enumerating peripherals, this is the easiest implementation.
+const NvOdmPeripheralConnectivity *NvOdmPeripheralGetGuid(NvU64 SearchGuid)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+        return NULL;
+
+    for (i=0; i<NumPeripherals; i++)
+    {
+        if (SearchGuid == pAllPeripherals[i].Guid)
+            return &pAllPeripherals[i];
+    }
+
+    return NULL;
+}
+
+static NvBool IsBusMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 offset,
+    NvU32 NumAttrs)
+{
+    NvU32 i, j;
+    NvBool IsMatch = NV_FALSE;
+
+    for (i=0; i<pPeriph->NumAddress; i++)
+    {
+        j = offset;
+        do
+        {
+            switch (pSearchAttrs[j])
+            {
+            case NvOdmPeripheralSearch_IoModule:
+                IsMatch = (pSearchVals[j] ==
+                           (NvU32)(pPeriph->AddressList[i].Interface));
+                break;
+            case NvOdmPeripheralSearch_Address:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Address);
+                break;
+            case NvOdmPeripheralSearch_Instance:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Instance);
+                break;
+            case NvOdmPeripheralSearch_PeripheralClass:
+            default:
+                NV_ASSERT(!"Bad Query!");
+                break;
+            }
+            j++;
+        } while (IsMatch && j<NumAttrs &&
+                 pSearchAttrs[j]!=NvOdmPeripheralSearch_IoModule);
+
+        if (IsMatch)
+        {
+            return NV_TRUE;
+        }
+    }
+    return NV_FALSE;
+}
+
+static NvBool IsPeripheralMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs)
+{
+    NvU32 i;
+    NvBool IsMatch = NV_TRUE;
+
+    for (i=0; i<NumAttrs && IsMatch; i++)
+    {
+        switch (pSearchAttrs[i])
+        {
+        case NvOdmPeripheralSearch_PeripheralClass:
+            IsMatch = (pSearchVals[i] == (NvU32)(pPeriph->Class));
+            break;
+        case NvOdmPeripheralSearch_IoModule:
+            IsMatch = IsBusMatch(pPeriph, pSearchAttrs, pSearchVals, i, NumAttrs);
+            break;
+        case NvOdmPeripheralSearch_Address:
+        case NvOdmPeripheralSearch_Instance:
+            // In correctly-formed searches, these parameters will be parsed by
+            // IsBusMatch, so we ignore them here.
+            break;
+        default:
+            NV_ASSERT(!"Bad search attribute!");
+            break;
+        }
+    }
+    return IsMatch;
+}
+
+NvU32 NvOdmPeripheralEnumerate(
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs,
+    NvU64 *pGuidList,
+    NvU32 NumGuids)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 Matches;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+    {
+        return 0;
+    }
+
+    if (!pSearchAttrs || !pSearchVals)
+    {
+        NumAttrs = 0;
+    }
+    for (i=0, Matches=0; i<NumPeripherals &&
+             (Matches < NumGuids || !pGuidList); i++)
+    {
+        if ( !NumAttrs || IsPeripheralMatch(&pAllPeripherals[i],
+                                            pSearchAttrs, pSearchVals,
+                                            NumAttrs) )
+        {
+            if (pGuidList)
+                pGuidList[Matches] = pAllPeripherals[i].Guid;
+            Matches++;
+        }
+    }
+    return Matches;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_gpio.c b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_gpio.c
new file mode 100644
index 000000000000..4700a8be7210
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_gpio.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+#include "nvodm_query_gpio.h"
+#include "nvodm_services.h"
+#include "nvrm_drf.h"
+#include <linux/input.h>
+
+#define NVODM_PORT(x) ((x) - 'a')
+
+static const NvOdmGpioPinInfo s_vi[] = {
+    {NVODM_PORT('i'), 6, NvOdmGpioPinActiveState_High}, // EN_VDDIO_SD
+};
+
+static const NvOdmGpioPinInfo s_display[] = {
+
+    /* Panel 0 -- sony vga */
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 4, NvOdmGpioPinActiveState_Low },
+    // this pin is not needed for ap15
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 1 -- samtek */
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 2 -- sharp wvga */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 3 -- sharp qvga */
+    { NVODM_PORT('n'), 6, NvOdmGpioPinActiveState_High },   // LCD_DC0
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },    // LCD_CS0
+    { NVODM_PORT('b'), 3, NvOdmGpioPinActiveState_Low },    // LCD_PCLK
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },    // LCD_PWR0
+    { NVODM_PORT('e'), 0, NvOdmGpioPinActiveState_High },   // LCD_D0
+    { NVODM_PORT('e'), 1, NvOdmGpioPinActiveState_High },   // LCD_D1
+    { NVODM_PORT('e'), 2, NvOdmGpioPinActiveState_High },   // LCD_D2
+    { NVODM_PORT('e'), 3, NvOdmGpioPinActiveState_High },   // LCD_D3
+    { NVODM_PORT('e'), 4, NvOdmGpioPinActiveState_High },   // LCD_D4
+    { NVODM_PORT('e'), 5, NvOdmGpioPinActiveState_High },   // LCD_D5
+    { NVODM_PORT('e'), 6, NvOdmGpioPinActiveState_High },   // LCD_D6
+    { NVODM_PORT('e'), 7, NvOdmGpioPinActiveState_High },   // LCD_D7
+    { NVODM_PORT('f'), 0, NvOdmGpioPinActiveState_High },   // LCD_D8
+    { NVODM_PORT('f'), 1, NvOdmGpioPinActiveState_High },   // LCD_D9
+    { NVODM_PORT('f'), 2, NvOdmGpioPinActiveState_High },   // LCD_D10
+    { NVODM_PORT('f'), 3, NvOdmGpioPinActiveState_High },   // LCD_D11
+    { NVODM_PORT('f'), 4, NvOdmGpioPinActiveState_High },   // LCD_D12
+    { NVODM_PORT('f'), 5, NvOdmGpioPinActiveState_High },   // LCD_D13
+    { NVODM_PORT('f'), 6, NvOdmGpioPinActiveState_High },   // LCD_D14
+    { NVODM_PORT('f'), 7, NvOdmGpioPinActiveState_High },   // LCD_D15
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_High },   // LCD_D19
+
+    /* Panel 4 -- auo */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 5 -- Harmony E1162 LVDS interface */
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_High },   // Enable (LVDS_SHTDN_N) (LO:OFF, HI:ON)
+    { NVODM_PORT('w'), 0, NvOdmGpioPinActiveState_High },   // EN_VDD_BL
+    { NVODM_PORT('d'), 4, NvOdmGpioPinActiveState_High },   // LCD_BL_EN
+    { NVODM_PORT('c'), 6, NvOdmGpioPinActiveState_High },   // EN_VDD_PNL
+    { NVODM_PORT('u'), 5, NvOdmGpioPinActiveState_High },   // LCD_BL_PWM
+};
+
+static const NvOdmGpioPinInfo s_hdmi[] =
+{
+    /* hdmi hot-plug interrupt pin */
+    { NVODM_PORT('n'), 7, NvOdmGpioPinActiveState_High },    // HDMI HPD
+};
+
+static const NvOdmGpioPinInfo s_sdio[] = {
+    {NVODM_PORT('i'), 5, NvOdmGpioPinActiveState_Low},    // Card Detect for SDIO instance 2
+    /* High for WP and low for read/write */
+    {NVODM_PORT('h'), 1, NvOdmGpioPinActiveState_High},    // Write Protect for SDIO instance 2
+};
+
+static const NvOdmGpioPinInfo s_Bluetooth[] = {
+    {NVODM_PORT('u'), 0, NvOdmGpioPinActiveState_Low}   // BT_RST#
+};
+
+static const NvOdmGpioPinInfo s_Wlan[] = {
+    {NVODM_PORT('k'), 5, NvOdmGpioPinActiveState_Low},  // WF_PWDN#
+    {NVODM_PORT('k'), 6, NvOdmGpioPinActiveState_Low}   // WF_RST#
+};
+
+static const NvOdmGpioPinInfo s_Power[] = {
+    // lid open/close, High = Lid Closed
+    {NVODM_PORT('u'), 5, NvOdmGpioPinActiveState_High},
+    // power button
+    {NVODM_PORT('v'), 2, NvOdmGpioPinActiveState_Low}
+};
+
+// Gpio based keypad
+static const NvOdmGpioPinKeyInfo s_GpioPinKeyInfo[] = {
+    {KEY_MENU, 10, NV_TRUE},
+    {KEY_HOME, 10, NV_TRUE},
+    {KEY_BACK, 10, NV_TRUE},
+    {KEY_VOLUMEUP, 10, NV_TRUE},
+    {KEY_VOLUMEDOWN, 10, NV_TRUE},
+};
+
+
+// Gpio based keypad
+static const NvOdmGpioPinInfo s_GpioKeyBoard[] = {
+    {NVODM_PORT('q'), 0, NvOdmGpioPinActiveState_Low, (void *)&s_GpioPinKeyInfo[0]},
+    {NVODM_PORT('q'), 1, NvOdmGpioPinActiveState_Low, (void *)&s_GpioPinKeyInfo[1]},
+    {NVODM_PORT('q'), 2, NvOdmGpioPinActiveState_Low, (void *)&s_GpioPinKeyInfo[2]},
+    {NVODM_PORT('q'), 3, NvOdmGpioPinActiveState_Low, (void *)&s_GpioPinKeyInfo[3]},
+    {NVODM_PORT('q'), 4, NvOdmGpioPinActiveState_Low, (void *)&s_GpioPinKeyInfo[4]},
+};
+
+static const NvOdmGpioPinInfo s_Battery[] = {
+    // Low Battery
+    {NVODM_PORT('w'), 3, NvOdmGpioPinActiveState_Low},
+};
+const NvOdmGpioPinInfo *NvOdmQueryGpioPinMap(NvOdmGpioPinGroup Group,
+    NvU32 Instance, NvU32 *pCount)
+{
+    switch (Group)
+    {
+        case NvOdmGpioPinGroup_Display:
+            *pCount = NV_ARRAY_SIZE(s_display);
+            return s_display;
+
+        case NvOdmGpioPinGroup_Hdmi:
+            *pCount = NV_ARRAY_SIZE(s_hdmi);
+            return s_hdmi;
+
+        case NvOdmGpioPinGroup_Sdio:
+            if (Instance == 2)
+            {
+                *pCount = NV_ARRAY_SIZE(s_sdio);
+                return s_sdio;
+            }
+            else
+            {
+                *pCount = 0;
+                return NULL;
+            }
+
+        case NvOdmGpioPinGroup_Bluetooth:
+            *pCount = NV_ARRAY_SIZE(s_Bluetooth);
+            return s_Bluetooth;
+
+        case NvOdmGpioPinGroup_Wlan:
+            *pCount = NV_ARRAY_SIZE(s_Wlan);
+            return s_Wlan;
+
+        case NvOdmGpioPinGroup_Vi:
+            *pCount = NV_ARRAY_SIZE(s_vi);
+            return s_vi;
+
+        case NvOdmGpioPinGroup_keypadMisc:
+                *pCount = NV_ARRAY_SIZE(s_GpioKeyBoard);
+                return s_GpioKeyBoard;
+
+        case NvOdmGpioPinGroup_Battery:
+            *pCount = NV_ARRAY_SIZE(s_Battery);
+            return s_Battery;
+
+        default:
+            *pCount = 0;
+            return NULL;
+    }
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_pinmux.c b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_pinmux.c
new file mode 100644
index 000000000000..dc9f04fa8223
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/nvodm_query_pinmux.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * This file implements the pin-mux configuration tables for each I/O module.
+ */
+
+// THESE SETTINGS ARE PLATFORM-SPECIFIC (not SOC-specific).
+// PLATFORM = Ventana
+
+#include "nvodm_query_pinmux.h"
+#include "nvassert.h"
+#include "nvodm_query.h"
+#include "nvodm_services.h"
+
+static const NvU32 s_NvOdmPinMuxConfig_Uart[] = {
+    0,
+    NvOdmUartPinMap_Config1,    // UART2, 2 lines
+    NvOdmUartPinMap_Config1,    // UART3, 4 lines
+    NvOdmUartPinMap_Config2,    // UART4, 4 lines
+    0                           // UART5
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spi[] = {
+    NvOdmSpiPinMap_Config4,
+    0,
+    0,
+    0,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Twc[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2c[] = {
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2cPmu[] = {
+    NvOdmI2cPmuPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ulpi[] = {
+    NvOdmUlpiPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Sdio[] = {
+    NvOdmSdioPinMap_Config1,
+    0,
+    NvOdmSdioPinMap_Config2,
+    NvOdmSdioPinMap_Config2,    // Personality 5 uses SDIO (disables NAND)
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hsi[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdcp[] = {
+    NvOdmHdcpPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdmi[] = {
+    NvOdmHdmiPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Pwm[] = {
+    NvOdmPwmPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ata[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Dap[] = {
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Kbd[] = {
+    NvOdmKbdPinMap_Config3
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_SyncNor[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Mio[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_ExternalClock[] = {
+    NvOdmExternalClockPinMap_Config2,
+    NvOdmExternalClockPinMap_Config2,
+    NvOdmExternalClockPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_VideoInput[] = {
+    NvOdmVideoInputPinMap_Config2,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Display[] = {
+    NvOdmDisplayPinMap_Config1,
+    0  // Only 1 display is connected to the LCD pins
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_BacklightPwm[] = {
+    0,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_OneWire[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_PciExpress[] = {
+    //NvOdmPciExpressPinMap_Config1,
+    0
+};
+
+void NvOdmQueryPinMux(
+    NvOdmIoModule IoModule,
+    const NvU32 **pPinMuxConfigTable,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+    case NvOdmIoModule_Display:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Display;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Display);
+        break;
+
+    case NvOdmIoModule_Dap:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dap;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dap);
+        break;
+
+    case NvOdmIoModule_Hdcp:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdcp;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdcp);
+        break;
+
+    case NvOdmIoModule_Hdmi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdmi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdmi);
+        break;
+
+    case NvOdmIoModule_I2c:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c);
+        break;
+
+    case NvOdmIoModule_I2c_Pmu:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2cPmu;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2cPmu);
+        break;
+
+    case NvOdmIoModule_Sdio:
+       *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio;
+       *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio);
+        break;
+
+    case NvOdmIoModule_Spi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spi);
+        break;
+
+    case NvOdmIoModule_Uart:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart);
+        break;
+
+    case NvOdmIoModule_ExternalClock:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_ExternalClock;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_ExternalClock);
+        break;
+
+    case NvOdmIoModule_BacklightPwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_BacklightPwm;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_BacklightPwm);
+        break;
+
+    case NvOdmIoModule_Pwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Pwm;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Pwm);
+        break;
+
+    case NvOdmIoModule_Ulpi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ulpi;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ulpi);
+        break;
+
+    case NvOdmIoModule_Kbd:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Kbd;
+        *pCount = NV_ARRAY_SIZE(s_NvOdmPinMuxConfig_Kbd);
+        break;
+
+    case NvOdmIoModule_PciExpress:
+    case NvOdmIoModule_Twc:
+    case NvOdmIoModule_Hsi:
+    case NvOdmIoModule_Ata:
+    case NvOdmIoModule_SyncNor:
+    case NvOdmIoModule_Mio:
+    case NvOdmIoModule_VideoInput:
+    case NvOdmIoModule_OneWire:
+        *pPinMuxConfigTable = NULL;
+        *pCount = 0;
+        break;
+
+    default:
+        *pCount = 0;
+        break;
+    }
+}
+
+void NvOdmQueryClockLimits(
+    NvOdmIoModule IoModule,
+    const NvU32 **pClockSpeedLimits,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+        default:
+            *pClockSpeedLimits = NULL;
+            *pCount = 0;
+            break;
+    }
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/subboards/nvodm_query_discovery_pm275_addresses.h b/arch/arm/mach-tegra/odm_kit/query/ventana/subboards/nvodm_query_discovery_pm275_addresses.h
new file mode 100644
index 000000000000..81a638444022
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/subboards/nvodm_query_discovery_pm275_addresses.h
@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database NvOdmIoAddress entries
+ *                 for the peripherals on PM275 module.
+ */
+
+#include "pmu/tps6586x/nvodm_pmu_tps6586x_supply_info_table.h"
+#include "tmon/adt7461/nvodm_tmon_adt7461_channel.h"
+#include "nvodm_tmon.h"
+
+
+// RTC voltage rail
+static const NvOdmIoAddress s_RtcAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO2 }  /* VDD_RTC -> LD02 */
+};
+
+// Core voltage rail
+static const NvOdmIoAddress s_CoreAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_DCD0 }  /* VDD_CORE -> SM0 */
+};
+
+// CPU voltage rail
+static const NvOdmIoAddress s_ffaCpuAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_DCD1 }  /* VDD_CPU -> SM1 */
+};
+
+// PLLA voltage rail
+static const NvOdmIoAddress s_PllAAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLM voltage rail
+static const NvOdmIoAddress s_PllMAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLP voltage rail
+static const NvOdmIoAddress s_PllPAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLC voltage rail
+static const NvOdmIoAddress s_PllCAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLE voltage rail
+static const NvOdmIoAddress s_PllEAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK } /* AVDD_PLLE -> VDD_1V05 */
+};
+
+// PLLU voltage rail
+static const NvOdmIoAddress s_PllUAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDD_PLLU -> LDO1 */
+};
+
+// PLLU1 voltage rail
+static const NvOdmIoAddress s_ffaPllU1Addresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDD_PLLU -> LDO1 */
+};
+
+// PLLS voltage rail
+static const NvOdmIoAddress s_PllSAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* PLL_S -> LDO1 */
+};
+
+// PLLHD voltage rail
+static const NvOdmIoAddress s_PllHdmiAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO8 } /* AVDD_HDMI_PLL -> LDO8 */
+};
+
+// OSC voltage rail
+static const NvOdmIoAddress s_VddOscAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* AVDD_OSC -> LDO4 */
+};
+
+// PLLX voltage rail
+static const NvOdmIoAddress s_PllXAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX -> LDO1 */
+};
+
+// PLL_USB voltage rail
+static const NvOdmIoAddress s_PllUsbAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* AVDD_USB_PLL -> derived from LDO3 (VDD_3V3) */
+};
+
+// SYS IO voltage rail
+static const NvOdmIoAddress s_VddSysAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_SYS -> LDO4 */
+};
+
+// USB voltage rail
+static const NvOdmIoAddress s_VddUsbAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* AVDD_USB -> derived from LDO3 (VDD_3V3) */
+};
+
+// HDMI voltage rail
+static const NvOdmIoAddress s_VddHdmiAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO7 } /* AVDD_HDMI -> LDO7 */
+};
+
+// MIPI voltage rail (DSI_CSI)
+static const NvOdmIoAddress s_VddMipiAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS72012PmuSupply_LDO  } /* AVDD_DSI_CSI -> VDD_1V2 */
+};
+
+// LCD voltage rail
+static const NvOdmIoAddress s_VddLcdAddresses[] =
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_LCD -> (LDO4PG) */
+};
+
+// Audio voltage rail
+static const NvOdmIoAddress s_VddAudAddresses[] =
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_AUDIO -> (LDO4PG) */
+};
+
+// DDR voltage rail
+static const NvOdmIoAddress s_VddDdrAddresses[] =
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 }  /* VDDIO_DDR -> (LDO4PG) */
+};
+
+// DDR_RX voltage rail
+static const NvOdmIoAddress s_VddDdrRxAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO9 }  /* VDDIO_RX_DDR(2.7-3.3) -> LDO9 */
+};
+
+// NAND voltage rail
+static const NvOdmIoAddress s_VddNandAddresses[] =
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 }  /* VDDIO_NAND_3V3 -> derived from LDO3 (VDD_3V3) */
+};
+
+// UART voltage rail
+static const NvOdmIoAddress s_VddUartAddresses[] =
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_UART -> (LDO4PG) */
+};
+
+// SDIO voltage rail
+static const NvOdmIoAddress s_VddSdioAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_SDIO -> derived from LDO3 (VDD_3V3) */
+};
+
+// VDAC voltage rail
+static const NvOdmIoAddress s_VddVdacAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 } /* AVDD_VDAC -> LDO6 */
+};
+
+// VI voltage rail
+static const NvOdmIoAddress s_VddViAddresses[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_VI -> derived from LDO3 (VDD_3V3) */
+};
+
+// BB voltage rail
+static const NvOdmIoAddress s_VddBbAddresses[] =
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_BB -> (LDO4PG) */
+};
+
+// Super power voltage rail for the SOC
+static const NvOdmIoAddress s_VddSocAddresses[]=
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_SoC } /* VDD SOC */
+};
+
+
+// PMU0
+static const NvOdmIoAddress s_Pmu0Addresses[] =
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x68 },
+};
+
+static const NvOdmIoAddress s_Vddio_Vid_En[] = {
+    { NvOdmIoModule_Gpio, 'v'-'a', 5 },
+};
+
+static const NvOdmIoAddress s_Vddio_Sd_En[] = {
+    { NvOdmIoModule_Gpio, 'i'-'a', 6 },
+};
+
+static const NvOdmIoAddress s_Vddio_Bl_En[] = {
+    { NvOdmIoModule_Gpio, 'w'-'a', 0 },
+};
+
+static const NvOdmIoAddress s_Vddio_Pnl_En[] = {
+    { NvOdmIoModule_Gpio, 'c'-'a', 6 },
+};
+
+// SPI1 for Spi Ethernet Kitl only
+static const NvOdmIoAddress s_SpiEthernetAddresses[] =
+{
+    { NvOdmIoModule_Spi, 0, 0 },
+    { NvOdmIoModule_Gpio, (NvU32)'c'-'a', 1 },  // DBQ_IRQ, Port C, Pin 1
+};
+
+// P1160 ULPI USB
+static const NvOdmIoAddress s_UlpiUsbAddresses[] =
+{
+    { NvOdmIoModule_ExternalClock, 1, 0 }, /* ULPI PHY Clock -> DAP_MCLK2 */
+};
+
+//  LVDS LCD Display
+static const NvOdmIoAddress s_LvdsDisplayAddresses[] =
+{
+    { NvOdmIoModule_Display, 0, 0 },
+    { NvOdmIoModule_I2c, 0x00, 0xA0 },
+    { NvOdmIoModule_Pwm, 0x00, 0x2 },
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4},     /* VDDIO_LCD (AON:VDD_1V8) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 },    /* VDD_LVDS (VDD_3V3) */
+};
+
+//  HDMI addresses based on Concorde 2 design
+static const NvOdmIoAddress s_HdmiAddresses[] =
+{
+    { NvOdmIoModule_Hdmi, 0, 0 },
+
+    // Display Data Channel (DDC) for Extended Display Identification
+    // Data (EDID)
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    // HDCP ROM
+    { NvOdmIoModule_I2c, 0x01, 0x74 },
+
+    /* AVDD_HDMI */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },   // VDDIO_HDMI
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO8 },            // AVDD_HDMI_PLL
+
+    /* lcd i/o rail (for hot plug pin) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },    // VDDIO_LCD (VDD_1V8)
+};
+
+static const NvOdmIoAddress s_HdmiHotplug[] =
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },
+};
+
+// CRT address based on Concorde 2 design
+static const NvOdmIoAddress s_CrtAddresses[] =
+{
+    { NvOdmIoModule_Crt, 0, 0 },
+
+    // Display Data Channel (DDC) for Extended Display Identification
+    // Data (EDID)
+    // FIXME: Disable this for now since it causes some TV not display.
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 },    // AVDD_VDAC
+
+    /* lcd rail (required for crt out) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },    // VDDIO_LCD (VDD_1V8)
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },   // VDDIO_VGA
+};
+
+static const NvOdmIoAddress s_ffaVideoDacAddresses[] =
+{
+    { NvOdmIoModule_Tvo, 0x00, 0x00 },
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 },    // AVDD_VDAC
+};
+
+// Sdio
+static const NvOdmIoAddress s_SdioAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x2,  0x0 },                      /* SD Memory on SD Bus */
+    { NvOdmIoModule_Sdio, 0x3,  0x0 },                      /* SD Memory on SD Bus */
+    { NvOdmIoModule_Vdd,  0x00, Ext_SWITCHPmuSupply_VDDIO_SD },   /* EN_VDDIO_SD */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_SDIO -> derived from LDO3 (VDD_3V3) */
+};
+
+static const NvOdmIoAddress s_UsbMuxAddress[] =
+{
+    {NvOdmIoModule_Usb, 1, 0}
+};
+
+static const NvOdmIoAddress s_Tmon0Addresses[] =
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x98 },                  /* I2C bus */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 },    /* TMON pwer rail -> LDO3 (VDD_3V3) */
+    { NvOdmIoModule_Gpio, (NvU32)'n'-'a', 6 },              /* GPIO Port N and Pin 6 */
+
+    /* Temperature zone mapping */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Core, ADT7461ChannelID_Remote },   /* TSENSOR */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Ambient, ADT7461ChannelID_Local }, /* TSENSOR */
+};
+
+// Bluetooth
+static const NvOdmIoAddress s_p1162BluetoothAddresses[] =
+{
+    { NvOdmIoModule_Uart, 0x2,  0x0 },                  // FIXME: Is this used?
+    { NvOdmIoModule_Gpio, (NvU32)'u'-'a', 0 },          /* BT_RST#: GPIO Port U and Pin 0 */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDHOSTIF_BT -> LDO4 (AON:VDD_1V8) */
+};
+
+// Wlan
+static const NvOdmIoAddress s_WlanAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x0, 0x0 },                      /* WLAN is on SD Bus */
+    { NvOdmIoModule_Gpio, 0xa, 0x5 },                      /* GPIO Port K and Pin 5 - WIFI_PWR*/
+    { NvOdmIoModule_Gpio, 0xa, 0x6 },                      /* GPIO Port K and Pin 6 - WIFI_RST */
+    { NvOdmIoModule_Vdd,  0x00, TPS6586xPmuSupply_LDO4 },  /* VDDIO_WLAN (AON:VDD_1V8) */
+    { NvOdmIoModule_Vdd,  0x00, Ext_TPS72012PmuSupply_LDO } /* VCORE_WIFI (VDD_1V2) */
+};
+
+// Audio Codec
+static const NvOdmIoAddress s_AudioCodecAddresses[] =
+{
+    { NvOdmIoModule_ExternalClock, 0, 0 },
+    { NvOdmIoModule_I2c, 0x00, 0x34 },
+    { NvOdmIoModule_Gpio, (NvU32)'w'-'a', 0x02 },
+};
+
+// TouchPanel
+static const NvOdmIoAddress s_TouchPanelAddresses[] =
+{
+    { NvOdmIoModule_I2c, 0x00, 0x06 }, /* I2C address (7-bit) 0x03<<1=0x06(8-bit)  */
+    { NvOdmIoModule_Gpio, (NvU32)'v'-'a', 0x06 }, /* GPIO Port v and Pin 6 */
+};
+
+static const NvOdmIoAddress s_AcceleroAddresses[] =
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x1E }, /* I2C address (7-bit) 0xF<<1 = 0x1E(8-bit) */
+    { NvOdmIoModule_Gpio, (NvU32)'n'-'a', 0x04 }, /* Gpio port N and Pin 4 */
+};
diff --git a/arch/arm/mach-tegra/odm_kit/query/ventana/subboards/nvodm_query_discovery_pm275_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/ventana/subboards/nvodm_query_discovery_pm275_peripherals.h
new file mode 100644
index 000000000000..272fd71a7d47
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/ventana/subboards/nvodm_query_discovery_pm275_peripherals.h
@@ -0,0 +1,444 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database Peripheral entries
+ *                 for the peripherals on PM275 module.
+ */
+// AP20 doesn't have PLL_D rail.
+// PLLD (NV reserved) / Use PLL_U
+{
+    NV_VDD_PLLD_ODM_ID,
+    s_PllUAddresses,
+    NV_ARRAY_SIZE(s_PllUAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// RTC (NV reserved)
+{
+    NV_VDD_RTC_ODM_ID,
+    s_RtcAddresses,
+    NV_ARRAY_SIZE(s_RtcAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CORE (NV reserved)
+{
+    NV_VDD_CORE_ODM_ID,
+    s_CoreAddresses,
+    NV_ARRAY_SIZE(s_CoreAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CPU (NV reserved)
+{
+    NV_VDD_CPU_ODM_ID,
+    s_ffaCpuAddresses,
+    NV_ARRAY_SIZE(s_ffaCpuAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLA (NV reserved)
+{
+    NV_VDD_PLLA_ODM_ID,
+    s_PllAAddresses,
+    NV_ARRAY_SIZE(s_PllAAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLM (NV reserved)
+{
+    NV_VDD_PLLM_ODM_ID,
+    s_PllMAddresses,
+    NV_ARRAY_SIZE(s_PllMAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLP (NV reserved)
+{
+    NV_VDD_PLLP_ODM_ID,
+    s_PllPAddresses,
+    NV_ARRAY_SIZE(s_PllPAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLC (NV reserved)
+{
+    NV_VDD_PLLC_ODM_ID,
+    s_PllCAddresses,
+    NV_ARRAY_SIZE(s_PllCAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLE (NV reserved)
+{
+    NV_VDD_PLLE_ODM_ID,
+    s_PllEAddresses,
+    NV_ARRAY_SIZE(s_PllEAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU (NV reserved)
+{
+    NV_VDD_PLLU_ODM_ID,
+    s_PllUAddresses,
+    NV_ARRAY_SIZE(s_PllUAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU1 (NV reserved)
+{
+    NV_VDD_PLLU1_ODM_ID,
+    s_ffaPllU1Addresses,
+    NV_ARRAY_SIZE(s_ffaPllU1Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLS (NV reserved)
+{
+    NV_VDD_PLLS_ODM_ID,
+    s_PllSAddresses,
+    NV_ARRAY_SIZE(s_PllSAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI PLL (NV reserved)
+{
+    NV_VDD_PLLHDMI_ODM_ID,
+    s_PllHdmiAddresses,
+    NV_ARRAY_SIZE(s_PllHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// OSC VDD (NV reserved)
+{
+    NV_VDD_OSC_ODM_ID,
+    s_VddOscAddresses,
+    NV_ARRAY_SIZE(s_VddOscAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLX (NV reserved)
+{
+    NV_VDD_PLLX_ODM_ID,
+    s_PllXAddresses,
+    NV_ARRAY_SIZE(s_PllXAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLL_USB (NV reserved)
+{
+    NV_VDD_PLL_USB_ODM_ID,
+    s_PllUsbAddresses,
+    NV_ARRAY_SIZE(s_PllUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// System IO VDD (NV reserved)
+{
+    NV_VDD_SYS_ODM_ID,
+    s_VddSysAddresses,
+    NV_ARRAY_SIZE(s_VddSysAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB VDD (NV reserved)
+{
+    NV_VDD_USB_ODM_ID,
+    s_VddUsbAddresses,
+    NV_ARRAY_SIZE(s_VddUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI VDD (NV reserved)
+{
+    NV_VDD_HDMI_ODM_ID,
+    s_VddHdmiAddresses,
+    NV_ARRAY_SIZE(s_VddHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Power for HDMI Hotplug
+{
+    NV_VDD_HDMI_INT_ID,
+    s_HdmiHotplug,
+    NV_ARRAY_SIZE(s_HdmiHotplug),
+    NvOdmPeripheralClass_Other,
+},
+
+// MIPI VDD (NV reserved) / AVDD_DSI_CSI
+{
+    NV_VDD_MIPI_ODM_ID,
+    s_VddMipiAddresses,
+    NV_ARRAY_SIZE(s_VddMipiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// LCD VDD (NV reserved)
+{
+    NV_VDD_LCD_ODM_ID,
+    s_VddLcdAddresses,
+    NV_ARRAY_SIZE(s_VddLcdAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// AUDIO VDD (NV reserved)
+{
+    NV_VDD_AUD_ODM_ID,
+    s_VddAudAddresses,
+    NV_ARRAY_SIZE(s_VddAudAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR VDD (NV reserved)
+{
+    NV_VDD_DDR_ODM_ID,
+    s_VddDdrAddresses,
+    NV_ARRAY_SIZE(s_VddDdrAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR_RX (NV reserved)
+{
+    NV_VDD_DDR_RX_ODM_ID,
+    s_VddDdrRxAddresses,
+    NV_ARRAY_SIZE(s_VddDdrRxAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// NAND VDD (NV reserved)
+{
+    NV_VDD_NAND_ODM_ID,
+    s_VddNandAddresses,
+    NV_ARRAY_SIZE(s_VddNandAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// UART VDD (NV reserved)
+{
+    NV_VDD_UART_ODM_ID,
+    s_VddUartAddresses,
+    NV_ARRAY_SIZE(s_VddUartAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// SDIO VDD (NV reserved)
+{
+    NV_VDD_SDIO_ODM_ID,
+    s_VddSdioAddresses,
+    NV_ARRAY_SIZE(s_VddSdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VDAC VDD (NV reserved)
+{
+    NV_VDD_VDAC_ODM_ID,
+    s_VddVdacAddresses,
+    NV_ARRAY_SIZE(s_VddVdacAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VI VDD (NV reserved)
+{
+    NV_VDD_VI_ODM_ID,
+    s_VddViAddresses,
+    NV_ARRAY_SIZE(s_VddViAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// BB VDD (NV reserved)
+{
+    NV_VDD_BB_ODM_ID,
+    s_VddBbAddresses,
+    NV_ARRAY_SIZE(s_VddBbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//SOC
+{
+    NV_VDD_SoC_ODM_ID,
+    s_VddSocAddresses,
+    NV_ARRAY_SIZE(s_VddSocAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  PMU0
+{
+    NV_ODM_GUID('t','p','s','6','5','8','6','x'),
+    s_Pmu0Addresses,
+    NV_ARRAY_SIZE(s_Pmu0Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PMU voltage rails enabled by AP GPIOs
+{
+    TPS_EXT_GUID(Ext_TPS2051BPmuSupply_VDDIO_VID),
+    s_Vddio_Vid_En,
+    NV_ARRAY_SIZE(s_Vddio_Vid_En),
+    NvOdmPeripheralClass_Other,
+},
+{
+    TPS_EXT_GUID(Ext_SWITCHPmuSupply_VDDIO_SD),
+    s_Vddio_Sd_En,
+    NV_ARRAY_SIZE(s_Vddio_Sd_En),
+    NvOdmPeripheralClass_Other,
+},
+{
+    TPS_EXT_GUID(Ext_SWITCHPmuSupply_VDD_BL),
+    s_Vddio_Bl_En,
+    NV_ARRAY_SIZE(s_Vddio_Bl_En),
+    NvOdmPeripheralClass_Other,
+},
+{
+    TPS_EXT_GUID(Ext_SWITCHPmuSupply_VDD_PNL),
+    s_Vddio_Pnl_En,
+    NV_ARRAY_SIZE(s_Vddio_Pnl_En),
+    NvOdmPeripheralClass_Other,
+},
+
+//  ENC28J60 SPI Ethernet module
+{
+    NV_ODM_GUID('e','n','c','2','8','j','6','0'),
+    s_SpiEthernetAddresses,
+    NV_ARRAY_SIZE(s_SpiEthernetAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  SMSC3317 ULPI USB PHY
+{
+    NV_ODM_GUID('s','m','s','c','3','3','1','7'),
+    s_UlpiUsbAddresses,
+    NV_ARRAY_SIZE(s_UlpiUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  LVDS LCD Display
+{
+    NV_ODM_GUID('L','V','D','S','W','S','V','G'),   // LVDS WSVGA panel
+    s_LvdsDisplayAddresses,
+    NV_ARRAY_SIZE(s_LvdsDisplayAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// HDMI (based on Concorde 2 design)
+{
+    NV_ODM_GUID('f','f','a','2','h','d','m','i'),
+    s_HdmiAddresses,
+    NV_ARRAY_SIZE(s_HdmiAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// CRT (based on Concorde 2 design)
+{
+    NV_ODM_GUID('f','f','a','_','_','c','r','t'),
+    s_CrtAddresses,
+    NV_ARRAY_SIZE(s_CrtAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// TV Out Video Dac
+{
+    NV_ODM_GUID('f','f','a','t','v','o','u','t'),
+    s_ffaVideoDacAddresses,
+    NV_ARRAY_SIZE(s_ffaVideoDacAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// Sdio
+{
+    NV_ODM_GUID('s','d','i','o','_','m','e','m'),
+    s_SdioAddresses,
+    NV_ARRAY_SIZE(s_SdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB Mux J7A1 and J6A1
+{
+   NV_ODM_GUID('u','s','b','m','x','J','7','6'),
+    s_UsbMuxAddress,
+    NV_ARRAY_SIZE(s_UsbMuxAddress),
+    NvOdmPeripheralClass_Other
+
+},
+
+// Temperature Monitor (TMON)
+{
+    NV_ODM_GUID('a','d','t','7','4','6','1',' '),
+    s_Tmon0Addresses,
+    NV_ARRAY_SIZE(s_Tmon0Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Bluetooth
+{
+    NV_ODM_GUID('b','l','u','t','o','o','t','h'),
+    s_p1162BluetoothAddresses,
+    NV_ARRAY_SIZE(s_p1162BluetoothAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Sdio wlan  on COMMs Module
+{
+    NV_ODM_GUID('s','d','i','o','w','l','a','n'),
+    s_WlanAddresses,
+    NV_ARRAY_SIZE(s_WlanAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+{
+    NV_ODM_GUID('w','o','l','f','8','9','0','3'),
+    s_AudioCodecAddresses,
+    NV_ARRAY_SIZE(s_AudioCodecAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Touch panel
+{
+    NV_ODM_GUID('p','a','n','j','i','t','_','0'),
+    s_TouchPanelAddresses,
+    NV_ARRAY_SIZE(s_TouchPanelAddresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// Accelerometer Module
+{
+    NV_ODM_GUID('k','x','t','f','9','-','4','0'),
+    s_AcceleroAddresses,
+    NV_ARRAY_SIZE(s_AcceleroAddresses),
+    NvOdmPeripheralClass_Other,
+},
+
+// NOTE: This list *must* end with a trailing comma.