diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-07-14 16:16:00 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-07-15 12:44:24 -0500 |
| commit | 46d896c4b76fa4877387e780b05883333f24f8d5 (patch) | |
| tree | 512c1107038bf1e4e2e6049a57a96bb1948a8919 /arch | |
| parent | 32866f4088a397d3586446b4e0c64bb740b8013f (diff) | |
ENGR00153158: MX51-Increase AHB_CLK to 66.5MHz if SDHC is active
Random failures can occur if SDHC clk is below AHB_CLK. So
ensure that ahb_clk is atleast 66.5MHz when SDHC is active.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx5/clock.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index 5c08b1d6d3c0..a57c666140e0 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -4514,6 +4514,11 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate; esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate; + esdhc1_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc2_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc3_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc4_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + ata_clk[1].secondary = &ahb_max_clk; clk_tree_init(); |