ENGR00131925-1 MX5 ssi: Add SSI3 support

Add ssi3 support for MX5.

According to manual, ssi3 clock should be same to ssi1 or ssi2.

Signed-off-by: Zeng Zhaoming <b32542@freescale.com>

5 files changed, 285 insertions, 5 deletions

diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index 2fe1d4d1b440..78e73fb14e28 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -2586,6 +2586,57 @@ static struct clk ssi2_clk[] = {
 	 },
 };
 
+static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg;
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+
+	if (parent == &ssi1_clk[0])
+		reg &= ~MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+	else if (parent == &ssi2_clk[0])
+		reg |= MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+	else {
+		printk(KERN_ERR"Set ssi3 clock parent failed!\n");
+		printk(KERN_ERR"ssi3 only support");
+		printk(KERN_ERR"ssi1 and ssi2 as parent clock\n");
+		return -1;
+	}
+
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+	return 0;
+}
+
+static struct clk ssi3_clk[] = {
+	{
+	 .id = 2,
+	 .parent = &ssi1_clk[0],
+	 .set_parent = _clk_ssi3_set_parent,
+	 .secondary = &ssi3_clk[1],
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	 .id = 2,
+	 .parent = &ipg_clk,
+	 .secondary = &ssi3_clk[2],
+	 .enable_reg = MXC_CCM_CCGR3,
+	 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+	 .enable = _clk_enable,
+	 .disable = _clk_disable,
+	 },
+	{
+	 .id = 2,
+	 .parent = &aips_tz2_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+	 .secondary = &emi_intr_clk,
+#else
+	 .secondary = &emi_fast_clk,
+#endif
+	 },
+};
+
 static unsigned long _clk_ssi_ext1_get_rate(struct clk *clk)
 {
 	u32 reg, prediv, podf;
@@ -4138,6 +4189,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "ssi_lp_apm_clk", ssi_lp_apm_clk),
 	_REGISTER_CLOCK("mxc_ssi.0", NULL, ssi1_clk[0]),
 	_REGISTER_CLOCK("mxc_ssi.1", NULL, ssi2_clk[0]),
+	_REGISTER_CLOCK("mxc_ssi.2", NULL, ssi3_clk[0]),
 	_REGISTER_CLOCK(NULL, "ssi_ext1_clk", ssi_ext1_clk),
 	_REGISTER_CLOCK(NULL, "ssi_ext2_clk", ssi_ext2_clk),
 	_REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
@@ -4449,6 +4501,12 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
 	__raw_writel(reg, MXC_CCM_CS2CDR);
 
+	/*
+	 * SSI3 has no clock divide register,
+	 * we always set SSI3 parent clock to SSI1 and freq same to SSI1
+	 */
+	clk_set_parent(&ssi3_clk[0], &ssi1_clk[0]);
+
 	/* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */
 	clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
 	clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7685a83083c4..986314c36559 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -731,6 +731,26 @@ struct platform_device mxc_ssi2_device = {
 	.resource = ssi2_resources,
 };
 
+static struct resource ssi3_resources[] = {
+	{
+		.start = SSI3_BASE_ADDR,
+		.end = SSI3_BASE_ADDR + 0x5C,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MXC_INT_SSI3,
+		.end = MXC_INT_SSI3,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device mxc_ssi3_device = {
+	.name = "mxc_ssi",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(ssi3_resources),
+	.resource = ssi3_resources,
+};
+
 static struct resource esai_resources[] = {
 	{
 		.start = ESAI_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/dma.c b/arch/arm/mach-mx5/dma.c
index 39b7776c6d15..1de75c4270f9 100644
--- a/arch/arm/mach-mx5/dma.c
+++ b/arch/arm/mach-mx5/dma.c
@@ -587,6 +587,174 @@ static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = {
 	.chnl_priority = 2,
 };
 
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_rx0_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_RXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_RX0_REG,
+			.peripheral_type = SSI,
+			.transfer_type = per_2_emi,
+			.event_id = DMA_REQ_SSI3_RX1,
+			.bd_number = 32,
+			.word_size = TRANSFER_8BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_RX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_tx0_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_TXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_TX0_REG,
+			.peripheral_type = SSI,
+			.transfer_type = emi_2_per,
+			.event_id = DMA_REQ_SSI3_TX1,
+			.bd_number = 32,
+			.word_size = TRANSFER_8BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_TX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_rx0_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_RXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_RX0_REG,
+			.peripheral_type = SSI,
+			.transfer_type = per_2_emi,
+			.event_id = DMA_REQ_SSI3_RX1,
+			.bd_number = 32,
+			.word_size = TRANSFER_16BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_RX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_tx0_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_TXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_TX0_REG,
+			.peripheral_type = SSI,
+			.transfer_type = emi_2_per,
+			.event_id = DMA_REQ_SSI3_TX1,
+			.bd_number = 32,
+			.word_size = TRANSFER_16BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_TX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_rx0_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_RXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_RX0_REG,
+			.peripheral_type = SSI,
+			.transfer_type = per_2_emi,
+			.event_id = DMA_REQ_SSI3_RX1,
+			.bd_number = 32,
+			.word_size = TRANSFER_32BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_RX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_tx0_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_TXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_TX0_REG,
+			.peripheral_type = SSI,
+			.transfer_type = emi_2_per,
+			.event_id = DMA_REQ_SSI3_TX1,
+			.bd_number = 32,
+			.word_size = TRANSFER_32BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_TX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_rx1_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_RXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_RX1_REG,
+			.peripheral_type = SSI,
+			.transfer_type = per_2_emi,
+			.event_id = DMA_REQ_SSI3_RX2,
+			.bd_number = 32,
+			.word_size = TRANSFER_8BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_RX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_tx1_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_TXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_TX1_REG,
+			.peripheral_type = SSI,
+			.transfer_type = emi_2_per,
+			.event_id = DMA_REQ_SSI3_TX2,
+			.bd_number = 32,
+			.word_size = TRANSFER_8BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_TX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_rx1_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_RXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_RX1_REG,
+			.peripheral_type = SSI,
+			.transfer_type = per_2_emi,
+			.event_id = DMA_REQ_SSI3_RX2,
+			.bd_number = 32,
+			.word_size = TRANSFER_16BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_RX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_tx1_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_TXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_TX1_REG,
+			.peripheral_type = SSI,
+			.transfer_type = emi_2_per,
+			.event_id = DMA_REQ_SSI3_TX2,
+			.bd_number = 32,
+			.word_size = TRANSFER_16BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_TX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_rx1_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_RXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_RX1_REG,
+			.peripheral_type = SSI,
+			.transfer_type = per_2_emi,
+			.event_id = DMA_REQ_SSI3_RX2,
+			.bd_number = 32,
+			.word_size = TRANSFER_32BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_RX,
+	.chnl_priority = 2,
+};
+
+static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_tx1_params = {
+	.chnl_params = {
+			.watermark_level = MXC_SSI_TXFIFO_WML,
+			.per_address = SSI3_BASE_ADDR + MXC_SSI_TX1_REG,
+			.peripheral_type = SSI,
+			.transfer_type = emi_2_per,
+			.event_id = DMA_REQ_SSI3_TX2,
+			.bd_number = 32,
+			.word_size = TRANSFER_32BIT,
+			},
+	.channel_num = MXC_DMA_CHANNEL_SSI3_TX,
+	.chnl_priority = 2,
+};
+
 static mxc_sdma_channel_params_t mxc_sdma_memory_params = {
 	.chnl_params = {
 			.peripheral_type = MEMORY,
@@ -1131,6 +1299,18 @@ static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = {
 	{MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params},
 	{MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params},
 	{MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params},
+	{MXC_DMA_SSI3_8BIT_RX0, &mxc_sdma_ssi3_8bit_rx0_params},
+	{MXC_DMA_SSI3_8BIT_TX0, &mxc_sdma_ssi3_8bit_tx0_params},
+	{MXC_DMA_SSI3_16BIT_RX0, &mxc_sdma_ssi3_16bit_rx0_params},
+	{MXC_DMA_SSI3_16BIT_TX0, &mxc_sdma_ssi3_16bit_tx0_params},
+	{MXC_DMA_SSI3_24BIT_RX0, &mxc_sdma_ssi3_24bit_rx0_params},
+	{MXC_DMA_SSI3_24BIT_TX0, &mxc_sdma_ssi3_24bit_tx0_params},
+	{MXC_DMA_SSI3_8BIT_RX1, &mxc_sdma_ssi3_8bit_rx1_params},
+	{MXC_DMA_SSI3_8BIT_TX1, &mxc_sdma_ssi3_8bit_tx1_params},
+	{MXC_DMA_SSI3_16BIT_RX1, &mxc_sdma_ssi3_16bit_rx1_params},
+	{MXC_DMA_SSI3_16BIT_TX1, &mxc_sdma_ssi3_16bit_tx1_params},
+	{MXC_DMA_SSI3_24BIT_RX1, &mxc_sdma_ssi3_24bit_rx1_params},
+	{MXC_DMA_SSI3_24BIT_TX1, &mxc_sdma_ssi3_24bit_tx1_params},
 	{MXC_DMA_MEMORY, &mxc_sdma_memory_params},
 	{MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params},
 	{MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params},
@@ -1186,6 +1366,13 @@ static int __init dma_fixups(void)
 	mxc_sdma_spdif_16bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX;
 	mxc_sdma_spdif_32bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX;
 
+	mxc_sdma_ssi3_8bit_tx1_params.chnl_params.event_id =
+						DMA_REQ_SSI3_TX2_MX53;
+	mxc_sdma_ssi3_16bit_tx1_params.chnl_params.event_id =
+						DMA_REQ_SSI3_TX2_MX53;
+	mxc_sdma_ssi3_24bit_tx1_params.chnl_params.event_id =
+						DMA_REQ_SSI3_TX2_MX53;
+
 	return 0;
 }
 arch_initcall(dma_fixups);
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index ce71b86f7eda..7b10512f892b 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -61,6 +61,18 @@ typedef enum mxc_dma_device {
 	MXC_DMA_SSI2_16BIT_TX1,
 	MXC_DMA_SSI2_24BIT_RX1,
 	MXC_DMA_SSI2_24BIT_TX1,
+	MXC_DMA_SSI3_8BIT_RX0,
+	MXC_DMA_SSI3_8BIT_TX0,
+	MXC_DMA_SSI3_16BIT_RX0,
+	MXC_DMA_SSI3_16BIT_TX0,
+	MXC_DMA_SSI3_24BIT_RX0,
+	MXC_DMA_SSI3_24BIT_TX0,
+	MXC_DMA_SSI3_8BIT_RX1,
+	MXC_DMA_SSI3_8BIT_TX1,
+	MXC_DMA_SSI3_16BIT_RX1,
+	MXC_DMA_SSI3_16BIT_TX1,
+	MXC_DMA_SSI3_24BIT_RX1,
+	MXC_DMA_SSI3_24BIT_TX1,
 	MXC_DMA_FIR_RX,
 	MXC_DMA_FIR_TX,
 	MXC_DMA_CSPI1_RX,
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 1127c6004f85..f407b024eaaf 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -288,14 +288,16 @@
 #define MXC_DMA_CHANNEL_UART5_TX	MXC_DMA_DYNAMIC_CHANNEL
 #define MXC_DMA_CHANNEL_MMC1		MXC_DMA_DYNAMIC_CHANNEL
 #define MXC_DMA_CHANNEL_MMC2		MXC_DMA_DYNAMIC_CHANNEL
-#define MXC_DMA_CHANNEL_SSI1_RX	MXC_DMA_DYNAMIC_CHANNEL
-#define MXC_DMA_CHANNEL_SSI1_TX	MXC_DMA_DYNAMIC_CHANNEL
-#define MXC_DMA_CHANNEL_SSI2_RX	MXC_DMA_DYNAMIC_CHANNEL
+#define MXC_DMA_CHANNEL_SSI1_RX		MXC_DMA_DYNAMIC_CHANNEL
+#define MXC_DMA_CHANNEL_SSI1_TX		MXC_DMA_DYNAMIC_CHANNEL
+#define MXC_DMA_CHANNEL_SSI2_RX		MXC_DMA_DYNAMIC_CHANNEL
 #ifdef CONFIG_SDMA_IRAM
-#define MXC_DMA_CHANNEL_SSI2_TX  (MXC_DMA_CHANNEL_IRAM + 1)
+#define MXC_DMA_CHANNEL_SSI2_TX		(MXC_DMA_CHANNEL_IRAM + 1)
 #else				/*CONFIG_SDMA_IRAM */
-#define MXC_DMA_CHANNEL_SSI2_TX	MXC_DMA_DYNAMIC_CHANNEL
+#define MXC_DMA_CHANNEL_SSI2_TX		MXC_DMA_DYNAMIC_CHANNEL
 #endif				/*CONFIG_SDMA_IRAM */
+#define MXC_DMA_CHANNEL_SSI3_RX		MXC_DMA_DYNAMIC_CHANNEL
+#define MXC_DMA_CHANNEL_SSI3_TX		MXC_DMA_DYNAMIC_CHANNEL
 #define MXC_DMA_CHANNEL_CSPI1_RX	MXC_DMA_DYNAMIC_CHANNEL
 #define MXC_DMA_CHANNEL_CSPI1_TX	MXC_DMA_DYNAMIC_CHANNEL
 #define MXC_DMA_CHANNEL_CSPI2_RX	MXC_DMA_DYNAMIC_CHANNEL
@@ -426,6 +428,7 @@
  */
 #define DMA_REQ_SSI3_TX1				47
 #define DMA_REQ_SSI3_RX1				46
+#define DMA_REQ_SSI3_TX2			DMA_REQ_SSI3_TX2_MX51
 #define DMA_REQ_SSI3_TX2_MX53			45
 #define DMA_REQ_SPDIF_MX51			45
 #define DMA_REQ_SSI3_RX2				44