diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2013-05-23 14:21:51 -0700 |
|---|---|---|
| committer | Gabby Lee <galee@nvidia.com> | 2013-07-30 19:25:52 -0700 |
| commit | 9e401658130324afba0725ef3908719853dae2c5 (patch) | |
| tree | c19be5c39536cd4e638d3e3aaa260e257ebe6bbc /arch | |
| parent | 5dcfe4f561bd8d1767e0938dfd7565b2b7718478 (diff) | |
arm: tegra: soctherm: fix heavy throttling on GPU zone
Fixed initialization of GPU throttling in level2 thermal control regs.
Bug 1169070
Reviewed-on: http://git-master/r/232300
(cherry picked from commit 51383ec7f26659c758a2f0ddf119c491e47737ff)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/246230
(cherry picked from commit dd538b8877a75e27ed41e0afd29ba9d3850102a3)
Change-Id: I121449b20fb987f61c6142e3783cd924f19a5bd6
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/255334
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra11_soctherm.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/tegra11_soctherm.c b/arch/arm/mach-tegra/tegra11_soctherm.c index 2def3f17a410..dfd21997a35a 100644 --- a/arch/arm/mach-tegra/tegra11_soctherm.c +++ b/arch/arm/mach-tegra/tegra11_soctherm.c @@ -71,10 +71,12 @@ static const int precision; /* default 0 -> low precision */ #define CTL_LVL0_CPU0_DN_THRESH_MASK 0xff #define CTL_LVL0_CPU0_EN_SHIFT 8 #define CTL_LVL0_CPU0_EN_MASK 0x1 +#define CTL_LVL0_CPU0_DEV_THROT_LIGHT 0x1 +#define CTL_LVL0_CPU0_DEV_THROT_HEAVY 0x2 #define CTL_LVL0_CPU0_CPU_THROT_SHIFT 5 #define CTL_LVL0_CPU0_CPU_THROT_MASK 0x3 -#define CTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1 -#define CTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2 +#define CTL_LVL0_CPU0_GPU_THROT_SHIFT 3 +#define CTL_LVL0_CPU0_GPU_THROT_MASK 0x3 #define CTL_LVL0_CPU0_MEM_THROT_SHIFT 2 #define CTL_LVL0_CPU0_MEM_THROT_MASK 0x1 #define CTL_LVL0_CPU0_STATUS_SHIFT 0 @@ -665,13 +667,16 @@ static inline void prog_hw_threshold(struct thermal_trip_info *trip_state, r = soctherm_readl(reg_off); r = REG_SET(r, CTL_LVL0_CPU0_UP_THRESH, trip_temp); - r = REG_SET(r, CTL_LVL0_CPU0_DN_THRESH, trip_temp); r = REG_SET(r, CTL_LVL0_CPU0_EN, 1); r = REG_SET(r, CTL_LVL0_CPU0_CPU_THROT, throt == THROTTLE_HEAVY ? - CTL_LVL0_CPU0_CPU_THROT_HEAVY : - CTL_LVL0_CPU0_CPU_THROT_LIGHT); + CTL_LVL0_CPU0_DEV_THROT_HEAVY : + CTL_LVL0_CPU0_DEV_THROT_LIGHT); + r = REG_SET(r, CTL_LVL0_CPU0_GPU_THROT, + throt == THROTTLE_HEAVY ? + CTL_LVL0_CPU0_DEV_THROT_HEAVY : + CTL_LVL0_CPU0_DEV_THROT_LIGHT); soctherm_writel(r, reg_off); } @@ -2197,10 +2202,16 @@ static int regs_show(struct seq_file *s, void *data) state = REG_GET(r, CTL_LVL0_CPU0_EN); seq_printf(s, "En(%d) ", state); state = REG_GET(r, CTL_LVL0_CPU0_CPU_THROT); - seq_printf(s, "Throt"); + seq_printf(s, "Throt-CPU"); + seq_printf(s, "(%s) ", state ? + state == CTL_LVL0_CPU0_DEV_THROT_LIGHT ? "L" : + state == CTL_LVL0_CPU0_DEV_THROT_HEAVY ? "H" : + "H+L" : "none"); + state = REG_GET(r, CTL_LVL0_CPU0_GPU_THROT); + seq_printf(s, "Throt-GPU"); seq_printf(s, "(%s) ", state ? - state == CTL_LVL0_CPU0_CPU_THROT_LIGHT ? "L" : - state == CTL_LVL0_CPU0_CPU_THROT_HEAVY ? "H" : + state == CTL_LVL0_CPU0_DEV_THROT_LIGHT ? "L" : + state == CTL_LVL0_CPU0_DEV_THROT_HEAVY ? "H" : "H+L" : "none"); state = REG_GET(r, CTL_LVL0_CPU0_STATUS); seq_printf(s, "Status(%s)\n", |