diff options
| author | Dong Aisheng <b29396@freescale.com> | 2014-11-11 21:04:07 +0800 |
|---|---|---|
| committer | Dong Aisheng <b29396@freescale.com> | 2015-01-21 18:23:34 +0800 |
| commit | 30522e42f4cbbb0f205f0cf58616e7698daec8eb (patch) | |
| tree | 869a2f77c5ddbf3a171fc745e9dc7d56a5fd10ed /arch | |
| parent | 3ec9d927209c823abbefc7b78a6c56b30ca5ddc1 (diff) | |
MLK-9833-1 ARM: imx6sx: only set can clock parent when M4 disabled
Since CAN device is allocated to run on M4 and handled by M4 if M4 is enabled,
so we do not set CAN parent clock when M4 is enabled.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit b41622a58d6e10e1be2618bf98fab6cc977d9985)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 6b3816edd352..053ee04d3b3a 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -638,9 +638,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) /* Set parent clock for vadc */ imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); - /* default parent of can_sel clock is invalid, manually set it here */ - imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); - /* Update gpu clock from default 528M to 720M */ imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); @@ -655,6 +652,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) imx_clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); imx_clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + if (!imx_src_is_m4_enabled()) + /* default parent of can_sel clock is invalid, manually set it here */ + imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); /* * Enable clocks only after both parent and rate are all initialized * as needed |