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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-12-10 20:38:32 +0800
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-01-11 09:25:36 -0800
commit2e971ed3bc0d1a089797f62ca171f58588d5f977 (patch)
treec82cef231896ef597cd61670ba01112f74513a6b /block
parentae4e74ce84045b33347bfa3291a891887e80e857 (diff)
ASoC: Fix WM8996 24.576MHz clock operation
commit 37d5993c5cc9bc83762ae1b5bd287438022e8afe upstream. Record the clock after the divider as that is what all SYSCLK users see. Without this the other clock configuration in the device comes out at half rate. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Change-Id: Ifd4d1165bc59b4cb35a3d30e43ebba442c67a68c Reviewed-on: http://git-master/r/74167 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com>
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