diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-10-30 15:20:50 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:34:54 +0800 |
| commit | d6215e9dedb997c336a2ad7c8560f10671325a5d (patch) | |
| tree | 1ef92352a0eb1871961de5878bd54bfda13ed9cc /drivers/ata | |
| parent | bc29ec384ee1c065822f1143a6ddcbf948683f90 (diff) | |
MLK-20125 ata: imx: add one ext_osc parameter for imx8qm ahci
Add one parameter to distinguish the different ref_clk
source, internal pll or the external osc.
NOTE: The value of the ext_osc should be aligned to the one
of the pcie's, since both of them share one ref_clk source.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/ata')
| -rw-r--r-- | drivers/ata/ahci_imx.c | 45 |
1 files changed, 33 insertions, 12 deletions
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index 09c5633db14a..96892576aeae 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -151,6 +151,7 @@ struct imx_ahci_priv { bool first_time; u32 phy_params; u32 imped_ratio; + u32 ext_osc; }; void *sg_io_buffer_hack; @@ -560,18 +561,32 @@ static int imx8_sata_enable(struct ahci_host_priv *hpriv) IMX8QM_PHY_MODE_MASK, IMX8QM_PHY_MODE_SATA); - /* - * bit0 rx ena 1, bit1 tx ena 0 - * bit12 PHY_X1_EPCS_SEL 1. - */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_RXENA, - IMX8QM_MISC_IOB_RXENA); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_TXENA, - 0); + if (imxpriv->ext_osc) { + dev_info(dev, "external osc is used.\n"); + /* + * bit0 rx ena 1, bit1 tx ena 0 + * bit12 PHY_X1_EPCS_SEL 1. + */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + IMX8QM_MISC_IOB_RXENA); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + 0); + } else { + dev_info(dev, "internal pll is used.\n"); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + 0); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + IMX8QM_MISC_IOB_TXENA); + + } regmap_update_bits(imxpriv->gpr, IMX8QM_CSR_MISC_OFFSET, IMX8QM_MISC_PHYX1_EPCS_SEL, @@ -1077,6 +1092,12 @@ static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv) struct platform_device *pdev = imxpriv->ahci_pdev; struct device_node *np = dev->of_node; + if (of_property_read_u32(np, "ext_osc", &imxpriv->ext_osc) < 0) { + dev_info(dev, "ext_osc is not specified.\n"); + /* Use the external osc as ref clk defaultly. */ + imxpriv->ext_osc = 1; + } + if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) { /* * Regarding to the differnet Hw designs, |