diff options
| author | venkatajagadish <vjagadish@nvidia.com> | 2013-06-04 16:35:55 +0530 |
|---|---|---|
| committer | Venkata Jagadish <vjagadish@nvidia.com> | 2013-11-18 21:59:05 -0800 |
| commit | 228b2d50afeaea7107c4e7e4d63060acef2c81ee (patch) | |
| tree | b25ac48e1e2fdd491c3d049abe95c00de8680426 /drivers/ata | |
| parent | f24d81b3752118a9f17396b09b1f4e9495d21a76 (diff) | |
SATA: tegra: Sw War for GEN2 SATA Drive
GEN2 tests fail when Idle Detect Circuit in Pad Model is Enabled
Bug 1294489
Change-Id: I5e5d86edf27daf58ef343b6796e6dc40dfba53bd
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/332302
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Diffstat (limited to 'drivers/ata')
| -rw-r--r-- | drivers/ata/ahci-tegra.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c index 661a0c79b06d..85091a39745a 100644 --- a/drivers/ata/ahci-tegra.c +++ b/drivers/ata/ahci-tegra.c @@ -93,6 +93,7 @@ static u32 tegra_ahci_idle_time = TEGRA_AHCI_DEFAULT_IDLE_TIME; #define FUSE_SATA_CALIB_MASK 0x3 #define T_SATA0_CFG_PHY_REG 0x120 +#define T_SATA0_CFG_PHY_SQUELCH_MASK (1 << 24) #define PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK (1 << 11) #define T_SATA0_CFG_POWER_GATE 0x4ac @@ -287,6 +288,15 @@ static u32 tegra_ahci_idle_time = TEGRA_AHCI_DEFAULT_IDLE_TIME; #define PLLE_SSCBYP (1 << 12) #define PLLE_INTERP_RESET (1 << 11) +#define SATA_AUX_RX_STAT_INT_0 0x110c +#define SATA_RX_STAT_INT_DISABLE (1 << 2) + +#define T_SATA0_NVOOB 0x114 +#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_SHIFT 24 +#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (3 << 24) +#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_SHIFT 26 +#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (3 << 26) + #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE /* create a work for handling the async transfers */ @@ -989,8 +999,14 @@ static int tegra_ahci_controller_init(struct tegra_ahci_host_priv *tegra_hpriv, */ val = scfg_readl(T_SATA0_CFG_PHY_REG); val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK; + val |= T_SATA0_CFG_PHY_SQUELCH_MASK; scfg_writel(val, T_SATA0_CFG_PHY_REG); + val = scfg_readl(T_SATA0_NVOOB); + val |= (1 << T_SATA0_NVOOB_SQUELCH_FILTER_MODE_SHIFT); + val |= (3 << T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_SHIFT); + scfg_writel(val, T_SATA0_NVOOB); + /* * WAR: Before enabling SATA PLL shutdown, lockdet needs to be ignored. * To ignore lockdet, T_SATA0_DBG0_OFFSET register bit 10 needs to @@ -1203,6 +1219,7 @@ static int tegra_ahci_resume(struct platform_device *pdev) { struct ata_host *host = dev_get_drvdata(&pdev->dev); int rc; + u32 val; dev_dbg(host->dev, "** entering %s: **\n", __func__); rc = tegra_ahci_controller_resume(pdev); @@ -1220,6 +1237,12 @@ static int tegra_ahci_resume(struct platform_device *pdev) if (rc) return rc; + val = misc_readl(SATA_AUX_RX_STAT_INT_0); + if (val && SATA_RX_STAT_INT_DISABLE) { + val &= ~SATA_RX_STAT_INT_DISABLE; + misc_writel(val, SATA_AUX_RX_STAT_INT_0); + } + ahci_init_controller(host); } @@ -2228,6 +2251,13 @@ static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class, static irqreturn_t tegra_ahci_interrupt(int irq, void *dev_instance) { irqreturn_t irq_retval; + u32 val; + + val = misc_readl(SATA_AUX_RX_STAT_INT_0); + if (!(val && SATA_RX_STAT_INT_DISABLE)) { + val |= SATA_RX_STAT_INT_DISABLE; + misc_writel(val, SATA_AUX_RX_STAT_INT_0); + } irq_retval = ahci_interrupt(irq, dev_instance); if (irq_retval == IRQ_NONE) |