diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2018-08-09 19:20:37 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:33:24 +0800 |
| commit | 8bd08b0e2540c6da0efd7b103f8c1acabdc0051e (patch) | |
| tree | 5e4eee7b464e4344cc2d0e199d271a8cae6b60f3 /drivers/clk/imx/clk-imx8mm.c | |
| parent | 1a1148ed54011ad5772ca209828db9e7a52c214b (diff) | |
MLK-19179: clk: imx8mm: change audio ahb and ipg clock to 400M
According to ADD, the audio ahb and ipg clock should be in 1:1 mode
and the frequency is 400MHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit ee175a8cea1a7d27954a73c3447bb16edd71f4c8)
Diffstat (limited to 'drivers/clk/imx/clk-imx8mm.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index e4e0c806b48b..4381f57dc8a0 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -956,7 +956,9 @@ static void __init imx8mm_clocks_init(struct device_node *ccm_node) clk_prepare_enable(clks[clks_init_on[i]]); } - clk_set_parent(clks[IMX8MM_CLK_AUDIO_AHB_SRC], clks[IMX8MM_SYS_PLL2_500M]); + clk_set_parent(clks[IMX8MM_CLK_AUDIO_AHB_SRC], clks[IMX8MM_SYS_PLL1_800M]); + clk_set_rate(clks[IMX8MM_CLK_AUDIO_AHB_DIV], 400000000); + clk_set_rate(clks[IMX8MM_CLK_IPG_AUDIO_ROOT], 400000000); /* increase NOC clock to design target */ clk_set_rate(clks[IMX8MM_SYS_PLL3], 750000000); |