diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-05-17 16:50:04 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:52 +0800 |
| commit | 8eed5747207baaa5858cd35315836ab2642fd222 (patch) | |
| tree | 9a2e4f9cc0955025dc9e1accbef85bb8b961aca6 /drivers/clk/imx/clk-imx8mm.c | |
| parent | 0211a9a727ce05fbb9362b7177dd258d9cb0325f (diff) | |
MLK-18298-3 clk: imx8mm: set the parent clks of pcie
Set the parent clks of pcie.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/clk/imx/clk-imx8mm.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mm.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index f8de523cb07c..6d761ea32f34 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -909,6 +909,8 @@ static void __init imx8mm_clocks_init(struct device_node *ccm_node) /* increase NOC clock to design target */ clk_set_rate(clks[IMX8MM_SYS_PLL3], 750000000); clk_set_parent(clks[IMX8MM_CLK_NOC_SRC], clks[IMX8MM_SYS_PLL3_OUT]); + clk_set_parent(clks[IMX8MM_CLK_PCIE1_CTRL_SRC], clks[IMX8MM_SYS_PLL2_250M]); + clk_set_parent(clks[IMX8MM_CLK_PCIE1_PHY_SRC], clks[IMX8MM_SYS_PLL2_100M]); pr_info("i.MX8MM clock driver init done\n"); } |