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| author | Otavio Salvador <otavio@ossystems.com.br> | 2022-05-19 11:02:10 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-19 11:02:10 -0300 |
| commit | b7007e1d615b8d4b71c28ebf790c5164fc4491d5 (patch) | |
| tree | 48c35f63dc1101d0d528b5d79c81849b99ca7c6d /drivers/clk/qcom/gdsc.c | |
| parent | 38955ef654554c94f4d91bafb9ef5c5f41a4c0f6 (diff) | |
| parent | 0e61b511dd8474280ba674590daa55f30433b7d4 (diff) | |
Merge pull request #565 from philschenker/update-to-5.4.193__update-to-2.3.7__5.4-2.3.x-imx
Update Patchlevel on Branch 5.4-2.3.x-imx from 5.4.161->5.4.193
Diffstat (limited to 'drivers/clk/qcom/gdsc.c')
| -rw-r--r-- | drivers/clk/qcom/gdsc.c | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index a250f59708d8..888965bb93ed 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved. */ #include <linux/bitops.h> @@ -31,9 +31,14 @@ #define CFG_GDSCR_OFFSET 0x4 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ -#define EN_REST_WAIT_VAL (0x2 << 20) -#define EN_FEW_WAIT_VAL (0x8 << 16) -#define CLK_DIS_WAIT_VAL (0x2 << 12) +#define EN_REST_WAIT_VAL 0x2 +#define EN_FEW_WAIT_VAL 0x8 +#define CLK_DIS_WAIT_VAL 0x2 + +/* Transition delay shifts */ +#define EN_REST_WAIT_SHIFT 20 +#define EN_FEW_WAIT_SHIFT 16 +#define CLK_DIS_WAIT_SHIFT 12 #define RETAIN_MEM BIT(14) #define RETAIN_PERIPH BIT(13) @@ -308,7 +313,18 @@ static int gdsc_init(struct gdsc *sc) */ mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; - val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; + + if (!sc->en_rest_wait_val) + sc->en_rest_wait_val = EN_REST_WAIT_VAL; + if (!sc->en_few_wait_val) + sc->en_few_wait_val = EN_FEW_WAIT_VAL; + if (!sc->clk_dis_wait_val) + sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL; + + val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT | + sc->en_few_wait_val << EN_FEW_WAIT_SHIFT | + sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT; + ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); if (ret) return ret; |