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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2016-02-22 11:43:39 +0000
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-05-11 11:21:12 +0200
commitfaaf496612c39c8ca6d46fec5a6af78b85689f65 (patch)
tree862f4482a5f48a0066387c7ada19d222d6a729e3 /drivers/clk
parentcf5281ef53856c5c9e4e9b0728805416502e466a (diff)
clk: qcom: msm8960: fix ce3_core clk enable register
commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream. This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 66c18bc97857..2c83c03309cb 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = {
.halt_reg = 0x2fdc,
.halt_bit = 5,
.clkr = {
- .enable_reg = 0x36c4,
+ .enable_reg = 0x36cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce3_core_clk",