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authorCaesar Wang <wxt@rock-chips.com>2015-09-25 10:14:55 +0800
committerDaniel Lezcano <daniel.lezcano@linaro.org>2015-12-15 09:41:11 +0100
commit23b8f81f3890edd06bcabdaac33ff5c087114c59 (patch)
tree2376e13d6189ef217909e983c13f42a2b6aea671 /drivers/clocksource/rockchip_timer.c
parent364eba4b3a58a3e9af5a1355f4131a58cd1f3b8d (diff)
clocksource/drivers/rockchip: Remove dsb() usage
The dsb() instruction is pointless in this code. Remove it. That also fixes the ARM64 compilation issue. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Tested-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'drivers/clocksource/rockchip_timer.c')
-rw-r--r--drivers/clocksource/rockchip_timer.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index b14716b62d63..8c77a529d0d4 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -49,14 +49,12 @@ static inline void __iomem *rk_base(struct clock_event_device *ce)
static inline void rk_timer_disable(struct clock_event_device *ce)
{
writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
- dsb();
}
static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
{
writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
rk_base(ce) + TIMER_CONTROL_REG);
- dsb();
}
static void rk_timer_update_counter(unsigned long cycles,
@@ -64,13 +62,11 @@ static void rk_timer_update_counter(unsigned long cycles,
{
writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
- dsb();
}
static void rk_timer_interrupt_clear(struct clock_event_device *ce)
{
writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
- dsb();
}
static inline int rk_timer_set_next_event(unsigned long cycles,