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authorArnd Bergmann <arnd@arndb.de>2013-06-20 01:43:19 +0200
committerArnd Bergmann <arnd@arndb.de>2013-06-20 01:43:19 +0200
commita44bde66bec168889c95bd1d0d15834b02387901 (patch)
tree70e8d2bbc26d72d51928e6aacb274829f835a5d1 /drivers/clocksource
parentef0a3402cccf75b43b1ed854f57fb11b54a1241a (diff)
parent50dbb4cfbc264b074759e8fb5d8e0c0496a1b072 (diff)
Merge tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx into next/dt
From Michal Simek: arm: Xilinx Zynq dt changes for v3.11 The branch contains: - DT uart handling cleanup - Support for zc706 and zed board - Removal of board compatible string * tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx: arm: dt: zynq: Add support for the zed platform arm: dt: zynq: Add support for the zc706 platform arm: dt: zynq: Use 'status' property for UART nodes arm: zynq: Remove board specific compatibility string clk: zynq: Remove deprecated clock code arm: zynq: Migrate platform to clock controller clk: zynq: Add clock controller driver clk: zynq: Factor out PLL driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/cadence_ttc_timer.c23
1 files changed, 18 insertions, 5 deletions
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 685bc60e210a..4cbe28c74631 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -51,6 +51,8 @@
#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
+#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
+
/*
* Setup the timers to use pre-scaling, using a fixed value for now that will
* work across most input frequency, but it may need to be more dynamic
@@ -396,8 +398,9 @@ static void __init ttc_timer_init(struct device_node *timer)
{
unsigned int irq;
void __iomem *timer_baseaddr;
- struct clk *clk;
+ struct clk *clk_cs, *clk_ce;
static int initialized;
+ int clksel;
if (initialized)
return;
@@ -421,14 +424,24 @@ static void __init ttc_timer_init(struct device_node *timer)
BUG();
}
- clk = of_clk_get_by_name(timer, "cpu_1x");
- if (IS_ERR(clk)) {
+ clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
+ clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+ clk_cs = of_clk_get(timer, clksel);
+ if (IS_ERR(clk_cs)) {
+ pr_err("ERROR: timer input clock not found\n");
+ BUG();
+ }
+
+ clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
+ clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+ clk_ce = of_clk_get(timer, clksel);
+ if (IS_ERR(clk_ce)) {
pr_err("ERROR: timer input clock not found\n");
BUG();
}
- ttc_setup_clocksource(clk, timer_baseaddr);
- ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
+ ttc_setup_clocksource(clk_cs, timer_baseaddr);
+ ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
}