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authorArnd Bergmann <arnd@arndb.de>2016-09-19 16:58:46 +0200
committerArnd Bergmann <arnd@arndb.de>2016-09-19 16:58:46 +0200
commit7a4c66d0c10ccde344d723e40e0a6b3542ed5bc2 (patch)
treeb84bf01b5ed53c24e78c71fce720361eadca8ecd /drivers/clocksource
parent70e058835562902a31ebac3e7bc70accd779c9c3 (diff)
parent8bc6bf178b671eb9b9fa806804f3990cb4c332aa (diff)
Merge tag 'samsung-drivers-4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers
Pull "Samsung drivers/soc update for v4.9" from Krzysztof Kozlowski: 1. Allow compile testing of exynos-mct clocksource driver on ARM64. 2. Document Exynos5433 PMU compatible (already used by clkout driver and more will be coming soon). * tag 'samsung-drivers-4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: EXYNOS: Add Exynos5433 PMU compatible clocksource: exynos_mct: Add the support for ARM64
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/Kconfig2
-rw-r--r--drivers/clocksource/exynos_mct.c4
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 567788664723..ec443c318c77 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -351,7 +351,7 @@ config CLKSRC_METAG_GENERIC
config CLKSRC_EXYNOS_MCT
bool "Exynos multi core timer driver" if COMPILE_TEST
- depends on ARM
+ depends on ARM || ARM64
help
Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 41840d02c331..8f3488b80896 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -223,6 +223,7 @@ static u64 notrace exynos4_read_sched_clock(void)
return exynos4_read_count_32();
}
+#if defined(CONFIG_ARM)
static struct delay_timer exynos4_delay_timer;
static cycles_t exynos4_read_current_timer(void)
@@ -231,14 +232,17 @@ static cycles_t exynos4_read_current_timer(void)
"cycles_t needs to move to 32-bit for ARM64 usage");
return exynos4_read_count_32();
}
+#endif
static int __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start();
+#if defined(CONFIG_ARM)
exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(&exynos4_delay_timer);
+#endif
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);