diff options
| author | Bai Ping <ping.bai@nxp.com> | 2016-02-23 13:20:37 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:24:33 +0800 |
| commit | b432dec150fab9c8413931f5c0c357998a12a3f9 (patch) | |
| tree | f469a3eed18225a71965523703b2c2a15b8e6508 /drivers/cpufreq | |
| parent | 71a2948f0d7706e03c5e83021b36b76d2692e388 (diff) | |
MLK-12623-01 cpufreq: imx: Add support for 700MHz setpoint in cpufreq
On i.MX6UL EVK board, we use a external GPIO DC regulator to control
the VDD_ARM_SOC_IN voltage, if default voltage is 1.4V when the system
is bootup. Per design team, when the highest setpoint freq is not
bigger than 528MHz, we can decrease this regulator voltage to 1.3V.
On i.MX6UL TO1.1, we add a 700MHz setpoint. When the highest setpoint
freq is 700MHz, the DC regulator should be at 1.4V to to cover the IR
drop.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'drivers/cpufreq')
| -rw-r--r-- | drivers/cpufreq/imx6q-cpufreq.c | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index ad153730585b..ac8c345e5d50 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -24,6 +24,7 @@ #define DC_VOLTAGE_MAX 1400000 #define FREQ_1P2_GHZ 1200000000 #define FREQ_396_MHZ 396000 +#define FREQ_696_MHZ 696000 static struct regulator *arm_reg; static struct regulator *pu_reg; @@ -50,6 +51,7 @@ static unsigned int transition_latency; static u32 *imx6_soc_volt; static u32 soc_opp_count; +static bool ignore_dc_reg; static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) { @@ -134,6 +136,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk); clk_set_parent(step_clk, secondary_sel_clk); clk_set_parent(pll1_sw_clk, step_clk); + if (freq_hz > clk_get_rate(pll2_bus_clk)) { + clk_set_rate(pll1_clk, new_freq * 1000); + clk_set_parent(pll1_sw_clk, pll1_sys_clk); + } } else { clk_set_parent(step_clk, pll2_pfd2_396m_clk); clk_set_parent(pll1_sw_clk, step_clk); @@ -235,11 +241,11 @@ static int imx6_cpufreq_pm_notify(struct notifier_block *nb, { switch (event) { case PM_SUSPEND_PREPARE: - if (!IS_ERR(dc_reg)) + if (!IS_ERR(dc_reg) && !ignore_dc_reg) regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MAX, 0); break; case PM_POST_SUSPEND: - if (!IS_ERR(dc_reg)) + if (!IS_ERR(dc_reg) && !ignore_dc_reg) regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); break; default: @@ -319,8 +325,6 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) } dc_reg = devm_regulator_get_optional(cpu_dev, "dc"); - if (!IS_ERR(dc_reg)) - regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); /* * soc_reg sync with arm_reg if arm shares the same regulator @@ -362,6 +366,15 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) goto out_free_opp; } + /* + * On i.MX6UL EVK board, if the SOC is run in overide frequency, + * the dc_regulator voltage should not be touched. + */ + if (freq_table[num - 1].frequency == FREQ_696_MHZ) + ignore_dc_reg = true; + if (!IS_ERR(dc_reg) && !ignore_dc_reg) + regulator_set_voltage_tol(dc_reg, DC_VOLTAGE_MIN, 0); + /* Make imx6_soc_volt array's size same as arm opp number */ imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL); if (imx6_soc_volt == NULL) { |